| Message ID | 20200326081847.5870-10-weijiang.yang@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Introduce support for guest CET feature | expand |
Hi Yang,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on kvm/linux-next]
[also build test ERROR on next-20200326]
[cannot apply to vhost/linux-next tip/auto-latest linus/master linux/master v5.6-rc7]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Yang-Weijiang/Introduce-support-for-guest-CET-feature/20200327-040801
base: https://git.kernel.org/pub/scm/virt/kvm/kvm.git linux-next
config: x86_64-randconfig-g001-20200327 (attached as .config)
compiler: gcc-7 (Debian 7.5.0-5) 7.5.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
In file included from include/linux/kvm_host.h:36:0,
from arch/x86/kvm/emulate.c:21:
arch/x86/kvm/emulate.c: In function 'check_cr_write':
>> arch/x86/include/asm/kvm_host.h:99:8: error: 'X86_CR4_CET' undeclared (first use in this function); did you mean 'X86_CR4_PCE'?
| X86_CR4_CET))
^
arch/x86/kvm/emulate.c:4206:3: note: in expansion of macro 'CR4_RESERVED_BITS'
CR4_RESERVED_BITS,
^~~~~~~~~~~~~~~~~
arch/x86/include/asm/kvm_host.h:99:8: note: each undeclared identifier is reported only once for each function it appears in
| X86_CR4_CET))
^
arch/x86/kvm/emulate.c:4206:3: note: in expansion of macro 'CR4_RESERVED_BITS'
CR4_RESERVED_BITS,
^~~~~~~~~~~~~~~~~
vim +99 arch/x86/include/asm/kvm_host.h
51
52 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
53 KVM_DIRTY_LOG_INITIALLY_SET)
54
55 /* x86-specific vcpu->requests bit members */
56 #define KVM_REQ_MIGRATE_TIMER KVM_ARCH_REQ(0)
57 #define KVM_REQ_REPORT_TPR_ACCESS KVM_ARCH_REQ(1)
58 #define KVM_REQ_TRIPLE_FAULT KVM_ARCH_REQ(2)
59 #define KVM_REQ_MMU_SYNC KVM_ARCH_REQ(3)
60 #define KVM_REQ_CLOCK_UPDATE KVM_ARCH_REQ(4)
61 #define KVM_REQ_LOAD_MMU_PGD KVM_ARCH_REQ(5)
62 #define KVM_REQ_EVENT KVM_ARCH_REQ(6)
63 #define KVM_REQ_APF_HALT KVM_ARCH_REQ(7)
64 #define KVM_REQ_STEAL_UPDATE KVM_ARCH_REQ(8)
65 #define KVM_REQ_NMI KVM_ARCH_REQ(9)
66 #define KVM_REQ_PMU KVM_ARCH_REQ(10)
67 #define KVM_REQ_PMI KVM_ARCH_REQ(11)
68 #define KVM_REQ_SMI KVM_ARCH_REQ(12)
69 #define KVM_REQ_MASTERCLOCK_UPDATE KVM_ARCH_REQ(13)
70 #define KVM_REQ_MCLOCK_INPROGRESS \
71 KVM_ARCH_REQ_FLAGS(14, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
72 #define KVM_REQ_SCAN_IOAPIC \
73 KVM_ARCH_REQ_FLAGS(15, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
74 #define KVM_REQ_GLOBAL_CLOCK_UPDATE KVM_ARCH_REQ(16)
75 #define KVM_REQ_APIC_PAGE_RELOAD \
76 KVM_ARCH_REQ_FLAGS(17, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
77 #define KVM_REQ_HV_CRASH KVM_ARCH_REQ(18)
78 #define KVM_REQ_IOAPIC_EOI_EXIT KVM_ARCH_REQ(19)
79 #define KVM_REQ_HV_RESET KVM_ARCH_REQ(20)
80 #define KVM_REQ_HV_EXIT KVM_ARCH_REQ(21)
81 #define KVM_REQ_HV_STIMER KVM_ARCH_REQ(22)
82 #define KVM_REQ_LOAD_EOI_EXITMAP KVM_ARCH_REQ(23)
83 #define KVM_REQ_GET_VMCS12_PAGES KVM_ARCH_REQ(24)
84 #define KVM_REQ_APICV_UPDATE \
85 KVM_ARCH_REQ_FLAGS(25, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
86
87 #define CR0_RESERVED_BITS \
88 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
89 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
90 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
91
92 #define CR4_RESERVED_BITS \
93 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
94 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
95 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \
96 | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \
97 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \
98 | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP \
> 99 | X86_CR4_CET))
100
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
On Thu, Mar 26, 2020 at 04:18:46PM +0800, Yang Weijiang wrote: > Set the feature bits so that CET capabilities can be seen > in guest via CPUID enumeration. Add CR4.CET bit support > in order to allow guest set CET master control bit(CR4.CET). > > Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> > --- > arch/x86/include/asm/kvm_host.h | 3 ++- > arch/x86/kvm/cpuid.c | 4 ++++ > 2 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h > index 2c944ad99692..5109c43c6981 100644 > --- a/arch/x86/include/asm/kvm_host.h > +++ b/arch/x86/include/asm/kvm_host.h > @@ -95,7 +95,8 @@ > | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ > | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ > | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ > - | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP)) > + | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP \ > + | X86_CR4_CET)) > > #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) > > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > index 25e9a11291b3..26ab959df92f 100644 > --- a/arch/x86/kvm/cpuid.c > +++ b/arch/x86/kvm/cpuid.c > @@ -366,6 +366,10 @@ void kvm_set_cpu_caps(void) > kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); > if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) > kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); > + if (boot_cpu_has(X86_FEATURE_IBT)) > + kvm_cpu_cap_set(X86_FEATURE_IBT); > + if (boot_cpu_has(X86_FEATURE_SHSTK)) > + kvm_cpu_cap_set(X86_FEATURE_SHSTK); This is the wrong way to advertise bits, the correct method is to declare the flag in the appriorate kvm_cpu_cap_mask() call. The manually handling is only needed when the feature bit diverges from kernel support, either because KVM allow a feature based purely on hardware support, e.g. LA57, or when emulating a feature based on a different similar feature, e.g. the STIBP/SSBD flags above. diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 6828be99b908..6262438f9527 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -329,7 +329,8 @@ void kvm_set_cpu_caps(void) F(AVX512VBMI) | F(LA57) | 0 /*PKU*/ | 0 /*OSPKE*/ | F(RDPID) | F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) | F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) | - F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ + F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ | + F(SHSTK) ); /* Set LA57 based on hardware capability. */ if (cpuid_ecx(7) & F(LA57)) @@ -338,7 +339,7 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_mask(CPUID_7_EDX, F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | - F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) + F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | F(IBT) ); > > kvm_cpu_cap_mask(CPUID_7_1_EAX, > F(AVX512_BF16) > -- > 2.17.2 >
For the shortlog, use something like KVM: x86: Enable CET virtualization and advertise CET to userspace It took me a while to find the patch that actually allowed setting CR4.CET because I was only scanning the shortlogs :-)
On Thu, Apr 23, 2020 at 09:56:31AM -0700, Sean Christopherson wrote: > On Thu, Mar 26, 2020 at 04:18:46PM +0800, Yang Weijiang wrote: > > Set the feature bits so that CET capabilities can be seen > > in guest via CPUID enumeration. Add CR4.CET bit support > > in order to allow guest set CET master control bit(CR4.CET). > > > > Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> > > --- > > arch/x86/include/asm/kvm_host.h | 3 ++- > > arch/x86/kvm/cpuid.c | 4 ++++ > > 2 files changed, 6 insertions(+), 1 deletion(-) > > > > diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h > > index 2c944ad99692..5109c43c6981 100644 > > --- a/arch/x86/include/asm/kvm_host.h > > +++ b/arch/x86/include/asm/kvm_host.h > > @@ -95,7 +95,8 @@ > > | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ > > | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ > > | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ > > - | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP)) > > + | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP \ > > + | X86_CR4_CET)) > > > > #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) > > > > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > > index 25e9a11291b3..26ab959df92f 100644 > > --- a/arch/x86/kvm/cpuid.c > > +++ b/arch/x86/kvm/cpuid.c > > @@ -366,6 +366,10 @@ void kvm_set_cpu_caps(void) > > kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); > > if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) > > kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); > > + if (boot_cpu_has(X86_FEATURE_IBT)) > > + kvm_cpu_cap_set(X86_FEATURE_IBT); > > + if (boot_cpu_has(X86_FEATURE_SHSTK)) > > + kvm_cpu_cap_set(X86_FEATURE_SHSTK); > > This is the wrong way to advertise bits, the correct method is to declare > the flag in the appriorate kvm_cpu_cap_mask() call. The manually handling > is only needed when the feature bit diverges from kernel support, either > because KVM allow a feature based purely on hardware support, e.g. LA57, or > when emulating a feature based on a different similar feature, e.g. the > STIBP/SSBD flags above. > > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > index 6828be99b908..6262438f9527 100644 > --- a/arch/x86/kvm/cpuid.c > +++ b/arch/x86/kvm/cpuid.c > @@ -329,7 +329,8 @@ void kvm_set_cpu_caps(void) > F(AVX512VBMI) | F(LA57) | 0 /*PKU*/ | 0 /*OSPKE*/ | F(RDPID) | > F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) | > F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) | > - F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ > + F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ | > + F(SHSTK) > ); > /* Set LA57 based on hardware capability. */ > if (cpuid_ecx(7) & F(LA57)) > @@ -338,7 +339,7 @@ void kvm_set_cpu_caps(void) > kvm_cpu_cap_mask(CPUID_7_EDX, > F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | > F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | > - F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) > + F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | F(IBT) > ); > Aah, thanks a lot for the explanation, will fix them. > > > > kvm_cpu_cap_mask(CPUID_7_1_EAX, > > F(AVX512_BF16) > > -- > > 2.17.2 > >
On Thu, Apr 23, 2020 at 09:58:12AM -0700, Sean Christopherson wrote: > For the shortlog, use something like > > KVM: x86: Enable CET virtualization and advertise CET to userspace > > It took me a while to find the patch that actually allowed setting CR4.CET > because I was only scanning the shortlogs :-) I always feel it's hard for me to get a good shortlog, sorry for the inconvenience :-(
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 2c944ad99692..5109c43c6981 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -95,7 +95,8 @@ | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ - | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP)) + | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP \ + | X86_CR4_CET)) #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 25e9a11291b3..26ab959df92f 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -366,6 +366,10 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); + if (boot_cpu_has(X86_FEATURE_IBT)) + kvm_cpu_cap_set(X86_FEATURE_IBT); + if (boot_cpu_has(X86_FEATURE_SHSTK)) + kvm_cpu_cap_set(X86_FEATURE_SHSTK); kvm_cpu_cap_mask(CPUID_7_1_EAX, F(AVX512_BF16)
Set the feature bits so that CET capabilities can be seen in guest via CPUID enumeration. Add CR4.CET bit support in order to allow guest set CET master control bit(CR4.CET). Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> --- arch/x86/include/asm/kvm_host.h | 3 ++- arch/x86/kvm/cpuid.c | 4 ++++ 2 files changed, 6 insertions(+), 1 deletion(-)