| Message ID | 20200326201610.31762-3-dafna.hirschfeld@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | media: staging: rkisp1: cap: various fixes for capture formats | expand |
On 3/26/20 5:16 PM, Dafna Hirschfeld wrote: > The register RKISP1_CIF_MI_XTD_FORMAT_CTRL is relevant only > for semiplanar formats, therefore the uv swap can be supported > through this register only for semiplanar formats. > > Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> Acked-by: Helen Koike <helen.koike@collabora.com> > --- > drivers/staging/media/rkisp1/rkisp1-capture.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/staging/media/rkisp1/rkisp1-capture.c b/drivers/staging/media/rkisp1/rkisp1-capture.c > index 84a3cf565106..fa2849209433 100644 > --- a/drivers/staging/media/rkisp1/rkisp1-capture.c > +++ b/drivers/staging/media/rkisp1/rkisp1-capture.c > @@ -37,6 +37,10 @@ > > #define RKISP1_MIN_BUFFERS_NEEDED 3 > > +#define RKISP1_IS_SEMI_PLANAR(write_format) \ > + (((write_format) == RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA) || \ > + ((write_format) == RKISP1_MI_CTRL_SP_WRITE_SPLA)) > + > enum rkisp1_plane { > RKISP1_PLANE_Y = 0, > RKISP1_PLANE_CB = 1, > @@ -429,7 +433,8 @@ static void rkisp1_mp_config(struct rkisp1_capture *cap) > cap->config->mi.cr_size_init); > > rkisp1_irq_frame_end_enable(cap); > - if (cap->pix.cfg->uv_swap) { > + if (RKISP1_IS_SEMI_PLANAR(cap->pix.cfg->write_format) && > + cap->pix.cfg->uv_swap) { > reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL); > > reg = reg | RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP; > @@ -466,7 +471,8 @@ static void rkisp1_sp_config(struct rkisp1_capture *cap) > rkisp1_write(rkisp1, cap->sp_y_stride, RKISP1_CIF_MI_SP_Y_LLENGTH); > > rkisp1_irq_frame_end_enable(cap); > - if (cap->pix.cfg->uv_swap) { > + if (RKISP1_IS_SEMI_PLANAR(cap->pix.cfg->write_format) && > + cap->pix.cfg->uv_swap) { > u32 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL); > > reg = reg | RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP; >
diff --git a/drivers/staging/media/rkisp1/rkisp1-capture.c b/drivers/staging/media/rkisp1/rkisp1-capture.c index 84a3cf565106..fa2849209433 100644 --- a/drivers/staging/media/rkisp1/rkisp1-capture.c +++ b/drivers/staging/media/rkisp1/rkisp1-capture.c @@ -37,6 +37,10 @@ #define RKISP1_MIN_BUFFERS_NEEDED 3 +#define RKISP1_IS_SEMI_PLANAR(write_format) \ + (((write_format) == RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA) || \ + ((write_format) == RKISP1_MI_CTRL_SP_WRITE_SPLA)) + enum rkisp1_plane { RKISP1_PLANE_Y = 0, RKISP1_PLANE_CB = 1, @@ -429,7 +433,8 @@ static void rkisp1_mp_config(struct rkisp1_capture *cap) cap->config->mi.cr_size_init); rkisp1_irq_frame_end_enable(cap); - if (cap->pix.cfg->uv_swap) { + if (RKISP1_IS_SEMI_PLANAR(cap->pix.cfg->write_format) && + cap->pix.cfg->uv_swap) { reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL); reg = reg | RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP; @@ -466,7 +471,8 @@ static void rkisp1_sp_config(struct rkisp1_capture *cap) rkisp1_write(rkisp1, cap->sp_y_stride, RKISP1_CIF_MI_SP_Y_LLENGTH); rkisp1_irq_frame_end_enable(cap); - if (cap->pix.cfg->uv_swap) { + if (RKISP1_IS_SEMI_PLANAR(cap->pix.cfg->write_format) && + cap->pix.cfg->uv_swap) { u32 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL); reg = reg | RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP;
The register RKISP1_CIF_MI_XTD_FORMAT_CTRL is relevant only for semiplanar formats, therefore the uv swap can be supported through this register only for semiplanar formats. Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> --- drivers/staging/media/rkisp1/rkisp1-capture.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)