[RESEND,6/7] drm/i915/bios: fill in DSC rc_model_size from VBT
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Message ID 20200327124229.26461-6-jani.nikula@intel.com
State New
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Series
  • [RESEND,1/7] drm/dsc: use rc_model_size from DSC config for PPS
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Commit Message

Jani Nikula March 27, 2020, 12:42 p.m. UTC
The VBT fields match the DPCD data, so use the same helper.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

Comments

Vandita Kulkarni April 8, 2020, 10:04 a.m. UTC | #1
> -----Original Message-----
> From: Jani Nikula <jani.nikula@intel.com>
> Sent: Friday, March 27, 2020 6:12 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Navare, Manasi D
> <manasi.d.navare@intel.com>; Kulkarni, Vandita <vandita.kulkarni@intel.com>
> Subject: [PATCH RESEND 6/7] drm/i915/bios: fill in DSC rc_model_size from
> VBT
> 
> The VBT fields match the DPCD data, so use the same helper.
> 
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c | 11 +++--------
>  1 file changed, 3 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 839124647202..a4ea0e6c3286 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2494,16 +2494,11 @@ static void fill_dsc(struct intel_crtc_state
> *crtc_state,
>  			      crtc_state->dsc.slice_count);
> 
>  	/*
> -	 * FIXME: Use VBT rc_buffer_block_size and rc_buffer_size for the
> -	 * implementation specific physical rate buffer size. Currently we use
> -	 * the required rate buffer model size calculated in
> -	 * drm_dsc_compute_rc_parameters() according to VESA DSC Annex E.
> -	 *
>  	 * The VBT rc_buffer_block_size and rc_buffer_size definitions
> -	 * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. The DP DSC
> -	 * implementation should also use the DPCD (or perhaps VBT for eDP)
> -	 * provided value for the buffer size.
> +	 * correspond to DP 1.4 DPCD offsets 0x62 and 0x63.
>  	 */
> +	vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc-
> >rc_buffer_block_size,
> +							    dsc-
> >rc_buffer_size);
Do we need to handle the invalid case here?

Regards
Vandita

> 
>  	/* FIXME: DSI spec says bpc + 1 for this one */
>  	vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc-
> >line_buffer_depth);
> --
> 2.20.1

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 839124647202..a4ea0e6c3286 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2494,16 +2494,11 @@  static void fill_dsc(struct intel_crtc_state *crtc_state,
 			      crtc_state->dsc.slice_count);
 
 	/*
-	 * FIXME: Use VBT rc_buffer_block_size and rc_buffer_size for the
-	 * implementation specific physical rate buffer size. Currently we use
-	 * the required rate buffer model size calculated in
-	 * drm_dsc_compute_rc_parameters() according to VESA DSC Annex E.
-	 *
 	 * The VBT rc_buffer_block_size and rc_buffer_size definitions
-	 * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. The DP DSC
-	 * implementation should also use the DPCD (or perhaps VBT for eDP)
-	 * provided value for the buffer size.
+	 * correspond to DP 1.4 DPCD offsets 0x62 and 0x63.
 	 */
+	vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size,
+							    dsc->rc_buffer_size);
 
 	/* FIXME: DSI spec says bpc + 1 for this one */
 	vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth);