| Message ID | 20200328030625.16428-4-chenyi.qiang@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | modify CPU model info | expand |
On 3/28/2020 11:06 AM, Chenyi Qiang wrote: > Add the SHA_NI and AVX512IFMA feature bits in FEAT_7_0_EBX, RDPID > feature bit in FEAT_7_0_ECX and FSRM feature bit in FEAT_7_0_EDX. > > Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com> > --- > target/i386/cpu.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index b01421c6bb..babb074abf 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -3552,6 +3552,16 @@ static X86CPUDefinition builtin_x86_defs[] = { > { /* end of list */ } > }, > }, > + { > + .version = 3, Maybe you need to make it as version = 4, since 3 is used to add ARCH_CAPABILITIES bits and the Patch is queued: https://lore.kernel.org/qemu-devel/20200323183936.GA3784@habkost.net/ > + .props = (PropValue[]) { > + { "sha-ni", "on" }, > + { "avx512ifma", "on" }, > + { "rdpid", "on" }, > + { "fsrm", "on" }, > + { /* end of list */ } > + }, > + }, > { /* end of list */ } > } > }, >
On Sat, 2020-03-28 at 11:06 +0800, Chenyi Qiang wrote: > Add the SHA_NI and AVX512IFMA feature bits in FEAT_7_0_EBX, RDPID > feature bit in FEAT_7_0_ECX and FSRM feature bit in FEAT_7_0_EDX. > > Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com> > --- > target/i386/cpu.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index b01421c6bb..babb074abf 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -3552,6 +3552,16 @@ static X86CPUDefinition builtin_x86_defs[] = { > { /* end of list */ } > }, > }, > + { > + .version = 3, > + .props = (PropValue[]) { > + { "sha-ni", "on" }, > + { "avx512ifma", "on" }, > + { "rdpid", "on" }, > + { "fsrm", "on" }, > + { /* end of list */ } > + }, > + }, > { /* end of list */ } I think these 4 new CPUIDs addition is to catch up latest https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf on updates. This is actually fix to previous v1 definitions. So my 2 cents: 1. add 1 more version: include v2's hle and rtm properties off 2. make the hle-rtm-disable inclusion version or this v3 default version of icelake. Anyway, v1 is not suitable for default choice. Then questions comes to how to make non-v1 default. Perhaps: diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 34b511f..d4eb3d6 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5453,7 +5453,7 @@ static void x86_register_cpudef_types(X86CPUDefinition *def) /* Unversioned model: */ m = g_new0(X86CPUModel, 1); m->cpudef = def; - m->version = CPU_VERSION_AUTO; + m->version = CPU_VERSION_LATEST; m->is_alias = true; x86_register_cpu_model_type(def->name, m); I think for builtin_x86_defs[] definitions, latest version is usually preferable/suitable. How would Paolo, Eduardo like it? > } > },
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b01421c6bb..babb074abf 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3552,6 +3552,16 @@ static X86CPUDefinition builtin_x86_defs[] = { { /* end of list */ } }, }, + { + .version = 3, + .props = (PropValue[]) { + { "sha-ni", "on" }, + { "avx512ifma", "on" }, + { "rdpid", "on" }, + { "fsrm", "on" }, + { /* end of list */ } + }, + }, { /* end of list */ } } },
Add the SHA_NI and AVX512IFMA feature bits in FEAT_7_0_EBX, RDPID feature bit in FEAT_7_0_ECX and FSRM feature bit in FEAT_7_0_EDX. Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com> --- target/i386/cpu.c | 10 ++++++++++ 1 file changed, 10 insertions(+)