ARM: dts: sun8i-h3: add opp table for mali gpu
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Message ID 20200328091632.12837-1-yuq825@gmail.com
State New
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Series
  • ARM: dts: sun8i-h3: add opp table for mali gpu
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Commit Message

Qiang Yu March 28, 2020, 9:16 a.m. UTC
OPP table vaule is get from orangepi lichee linux-3.4
kernel driver.

Signed-off-by: Qiang Yu <yuq825@gmail.com>
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

Comments

Maxime Ripard March 30, 2020, 5:53 p.m. UTC | #1
Hi,

On Sat, Mar 28, 2020 at 05:16:32PM +0800, Qiang Yu wrote:
> OPP table vaule is get from orangepi lichee linux-3.4
> kernel driver.
>
> Signed-off-by: Qiang Yu <yuq825@gmail.com>

Thanks!

I've fixed up the value typo, sorted the opp table according to its
node name, and added some new lines after each OPP node. This will be
part of 5.8.

Maxime

Patch
diff mbox series

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 20217e2ca4d3..53ef9a18e953 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -128,6 +128,23 @@ 
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
+	gpu_opp_table: gpu-opp-table {
+		compatible = "operating-points-v2";
+
+		opp-120000000 {
+			opp-hz = /bits/ 64 <120000000>;
+		};
+		opp-312000000 {
+			opp-hz = /bits/ 64 <312000000>;
+		};
+		opp-432000000 {
+			opp-hz = /bits/ 64 <432000000>;
+		};
+		opp-576000000 {
+			opp-hz = /bits/ 64 <576000000>;
+		};
+	};
+
 	soc {
 		deinterlace: deinterlace@1400000 {
 			compatible = "allwinner,sun8i-h3-deinterlace";
@@ -205,8 +222,7 @@ 
 			clock-names = "bus", "core";
 			resets = <&ccu RST_BUS_GPU>;
 
-			assigned-clocks = <&ccu CLK_GPU>;
-			assigned-clock-rates = <384000000>;
+			operating-points-v2 = <&gpu_opp_table>;
 		};
 
 		ths: thermal-sensor@1c25000 {