| Message ID | 20200328140232.17278-1-changbin.du@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/arm: fix incorrect current EL bug in aarch32 exception emulation | expand |
On 3/28/20 7:02 AM, Changbin Du wrote: > The arm_current_el() should be invoked after mode switching. Otherwise, we > get a wrong current EL value, since current EL is also determined by > current mode. > > Fixes: 4a2696c0d4 ("target/arm: Set PAN bit as required on exception entry") > Signed-off-by: Changbin Du <changbin.du@gmail.com> > --- > target/arm/helper.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
Hi, Peter, Could you take this fix as high priority? This bug has made qemu-system-arm broken. On Sat, Mar 28, 2020 at 10:02:32PM +0800, Changbin Du wrote: > The arm_current_el() should be invoked after mode switching. Otherwise, we > get a wrong current EL value, since current EL is also determined by > current mode. > > Fixes: 4a2696c0d4 ("target/arm: Set PAN bit as required on exception entry") > Signed-off-by: Changbin Du <changbin.du@gmail.com> > --- > target/arm/helper.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index b7b6887241..163c91a1cc 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -9172,7 +9172,6 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, > > /* Change the CPU state so as to actually take the exception. */ > switch_mode(env, new_mode); > - new_el = arm_current_el(env); > > /* > * For exceptions taken to AArch32 we must clear the SS bit in both > @@ -9184,6 +9183,10 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, > env->condexec_bits = 0; > /* Switch to the new mode, and to the correct instruction set. */ > env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; > + > + /* This must be after mode switching. */ > + new_el = arm_current_el(env); > + > /* Set new mode endianness */ > env->uncached_cpsr &= ~CPSR_E; > if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { > -- > 2.25.1 >
On Sat, 28 Mar 2020 at 14:02, Changbin Du <changbin.du@gmail.com> wrote: > > The arm_current_el() should be invoked after mode switching. Otherwise, we > get a wrong current EL value, since current EL is also determined by > current mode. > > Fixes: 4a2696c0d4 ("target/arm: Set PAN bit as required on exception entry") > Signed-off-by: Changbin Du <changbin.du@gmail.com> > --- > target/arm/helper.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index b7b6887241..163c91a1cc 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -9172,7 +9172,6 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, > > /* Change the CPU state so as to actually take the exception. */ > switch_mode(env, new_mode); > - new_el = arm_current_el(env); > > /* > * For exceptions taken to AArch32 we must clear the SS bit in both > @@ -9184,6 +9183,10 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, > env->condexec_bits = 0; > /* Switch to the new mode, and to the correct instruction set. */ > env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; > + > + /* This must be after mode switching. */ > + new_el = arm_current_el(env); > + > /* Set new mode endianness */ > env->uncached_cpsr &= ~CPSR_E; > if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { > -- > 2.25.1 Applied to target-arm.next, thanks. -- PMM
diff --git a/target/arm/helper.c b/target/arm/helper.c index b7b6887241..163c91a1cc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9172,7 +9172,6 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, /* Change the CPU state so as to actually take the exception. */ switch_mode(env, new_mode); - new_el = arm_current_el(env); /* * For exceptions taken to AArch32 we must clear the SS bit in both @@ -9184,6 +9183,10 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, env->condexec_bits = 0; /* Switch to the new mode, and to the correct instruction set. */ env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; + + /* This must be after mode switching. */ + new_el = arm_current_el(env); + /* Set new mode endianness */ env->uncached_cpsr &= ~CPSR_E; if (env->cp15.sctlr_el[new_el] & SCTLR_EE) {
The arm_current_el() should be invoked after mode switching. Otherwise, we get a wrong current EL value, since current EL is also determined by current mode. Fixes: 4a2696c0d4 ("target/arm: Set PAN bit as required on exception entry") Signed-off-by: Changbin Du <changbin.du@gmail.com> --- target/arm/helper.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)