drm/i915/selftests: Check timeout before flush and cond checks
diff mbox series

Message ID 20200330121644.25277-1-chris@chris-wilson.co.uk
State New
Headers show
Series
  • drm/i915/selftests: Check timeout before flush and cond checks
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Commit Message

Chris Wilson March 30, 2020, 12:16 p.m. UTC
Allow a bit of leniency for the CPU scheduler to be distracted while we
flush the tasklet and so ensure that we always check the status of the
request once more before timing out.

v2: Wait until the HW acked the submit, and we do any secondary actions
for the submit (e.g. timeslices)

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.auld@intel.com>
---
 drivers/gpu/drm/i915/gt/selftest_lrc.c | 30 ++++++++++++++++++--------
 1 file changed, 21 insertions(+), 9 deletions(-)

Comments

Matthew Auld March 30, 2020, 1:44 p.m. UTC | #1
On 30/03/2020 13:16, Chris Wilson wrote:
> Allow a bit of leniency for the CPU scheduler to be distracted while we
> flush the tasklet and so ensure that we always check the status of the
> request once more before timing out.
> 
> v2: Wait until the HW acked the submit, and we do any secondary actions
> for the submit (e.g. timeslices)
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Matthew Auld March 30, 2020, 1:48 p.m. UTC | #2
On Mon, 30 Mar 2020 at 13:17, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>
> Allow a bit of leniency for the CPU scheduler to be distracted while we
> flush the tasklet and so ensure that we always check the status of the
> request once more before timing out.
>
> v2: Wait until the HW acked the submit, and we do any secondary actions
> for the submit (e.g. timeslices)
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Matthew Auld <matthew.auld@intel.com>

Rejecting mails again.
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Chris Wilson March 30, 2020, 1:51 p.m. UTC | #3
Quoting Matthew Auld (2020-03-30 14:48:52)
> On Mon, 30 Mar 2020 at 13:17, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> >
> > Allow a bit of leniency for the CPU scheduler to be distracted while we
> > flush the tasklet and so ensure that we always check the status of the
> > request once more before timing out.
> >
> > v2: Wait until the HW acked the submit, and we do any secondary actions
> > for the submit (e.g. timeslices)
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Matthew Auld <matthew.auld@intel.com>
> 
> Rejecting mails again.
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>

But now I've told the list not to remove me from the CC, so at least I'm
now getting the ml copy :(
-Chris

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 6f06ba750a0a..dd6c63a2fb96 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -68,26 +68,38 @@  static void engine_heartbeat_enable(struct intel_engine_cs *engine,
 	engine->props.heartbeat_interval_ms = saved;
 }
 
+static bool is_active(struct i915_request *rq)
+{
+	if (i915_request_is_active(rq))
+		return true;
+
+	if (i915_request_on_hold(rq))
+		return true;
+
+	return false;
+}
+
 static int wait_for_submit(struct intel_engine_cs *engine,
 			   struct i915_request *rq,
 			   unsigned long timeout)
 {
 	timeout += jiffies;
 	do {
-		cond_resched();
-		intel_engine_flush_submission(engine);
+		bool done = time_after(jiffies, timeout);
 
-		if (READ_ONCE(engine->execlists.pending[0]))
-			continue;
-
-		if (i915_request_is_active(rq))
+		if (i915_request_completed(rq)) /* that was quick! */
 			return 0;
 
-		if (i915_request_started(rq)) /* that was quick! */
+		/* Wait until the HW has acknowleged the submission (or err) */
+		intel_engine_flush_submission(engine);
+		if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq))
 			return 0;
-	} while (time_before(jiffies, timeout));
 
-	return -ETIME;
+		if (done)
+			return -ETIME;
+
+		cond_resched();
+	} while (1);
 }
 
 static int wait_for_reset(struct intel_engine_cs *engine,