From patchwork Mon Mar 30 23:33:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 11466479 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2E3EA913 for ; Mon, 30 Mar 2020 23:31:50 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 15BF220771 for ; Mon, 30 Mar 2020 23:31:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 15BF220771 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2E4656E4D7; Mon, 30 Mar 2020 23:31:48 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 46E886E4E3 for ; Mon, 30 Mar 2020 23:31:47 +0000 (UTC) IronPort-SDR: +AiHlTm4ochIpla7LV+turUZQYk1LpxbvGFWNMil7lC6lRFmuI2xB869WqGz+UunZtzIUckusk uMPV1dZm1ffA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2020 16:31:42 -0700 IronPort-SDR: qqiLIPBbrNovt1JYcTE6uDUAdhoU194k6EBDFEY1jJBpB7noomQEb8JStIPMbQxxzkJZiCNL7L y6vFMTSKoR8A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,326,1580803200"; d="scan'208";a="242190311" Received: from josouza-mobl2.jf.intel.com (HELO josouza-MOBL2.intel.com) ([10.24.15.8]) by orsmga008.jf.intel.com with ESMTP; 30 Mar 2020 16:31:42 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Mon, 30 Mar 2020 16:33:03 -0700 Message-Id: <20200330233304.406215-2-jose.souza@intel.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200330233304.406215-1-jose.souza@intel.com> References: <20200330233304.406215-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/3] drm/i915/psr: Implement WA 1130 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Render modifications could not trigger PSR exit this WA fixes it. BSpec: 21664 Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index abb37437ff5d..2608c7e47aca 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4137,6 +4137,7 @@ enum { #define TGL_VRH_GATING_DIS REG_BIT(31) #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) +#define BXT_DPFC_GATING_DIS (1 << 31) #define BXT_GMBUS_GATING_DIS (1 << 14) #define _CLKGATE_DIS_PSL_A 0x46520 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 8375054ba27d..02184888d193 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -139,6 +139,10 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) * application, using batch buffers or any other means. */ I915_WRITE(RM_TIMEOUT, MMIO_TIMEOUT_US(950)); + + /* WA 1130 */ + I915_WRITE(GEN9_CLKGATE_DIS_4, + I915_READ(GEN9_CLKGATE_DIS_4) | BXT_DPFC_GATING_DIS); } static void glk_init_clock_gating(struct drm_i915_private *dev_priv) @@ -152,6 +156,10 @@ static void glk_init_clock_gating(struct drm_i915_private *dev_priv) */ I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | PWM1_GATING_DIS | PWM2_GATING_DIS); + + /* WA 1130 */ + I915_WRITE(GEN9_CLKGATE_DIS_4, + I915_READ(GEN9_CLKGATE_DIS_4) | BXT_DPFC_GATING_DIS); } static void pnv_get_mem_freq(struct drm_i915_private *dev_priv)