From patchwork Tue Mar 31 06:51:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryder Lee X-Patchwork-Id: 11466777 X-Patchwork-Delegate: nbd@nbd.name Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E2BCF912 for ; Tue, 31 Mar 2020 06:51:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C17A720748 for ; Tue, 31 Mar 2020 06:51:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="e0pjuefH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729968AbgCaGvy (ORCPT ); Tue, 31 Mar 2020 02:51:54 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:15083 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729918AbgCaGvx (ORCPT ); Tue, 31 Mar 2020 02:51:53 -0400 X-UUID: 006bba34ee6e4058afd77f1a9cacc190-20200331 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=X0OcyMvL4lbrg36Mk7oc4dDFTS47i4dhzRfE8BnWJPY=; b=e0pjuefH4LBBOaf69KOvQC2jlL8ddbwbVAK2zY/rPkbPiDIwlTPLitU5ep5SyFascGU8WVl8BHFaj6JSUOs33kKirsnk2N5EArdjBURte9Xama95FVC90tn11lY4VB/6CaGxnMNgGntVqTnw5xgMQPoO/+LOunrgdyaUdHOr/5A=; X-UUID: 006bba34ee6e4058afd77f1a9cacc190-20200331 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 58095262; Tue, 31 Mar 2020 14:51:43 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 31 Mar 2020 14:51:38 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 31 Mar 2020 14:51:38 +0800 From: Ryder Lee To: Felix Fietkau , Lorenzo Bianconi CC: Shayne Chen , Sean Wang , , , Ryder Lee Subject: [PATCH 2/4] mt76: mt7615: enable aggr_stats for both phy Date: Tue, 31 Mar 2020 14:51:36 +0800 Message-ID: <5f658e6a42f653299db86244942618730ffb9926.1585636614.git.ryder.lee@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <1fc90ec2a64d062ac7264aaa3dd158f2282ad7b8.1585636614.git.ryder.lee@mediatek.com> References: <1fc90ec2a64d062ac7264aaa3dd158f2282ad7b8.1585636614.git.ryder.lee@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 07D14E5CF4D800D171A703094CC85C8C5D681E1C11756252B4BC06F32B9DEBC62000:8 X-MTK: N Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org Use bottom half of aggr_stats for second phy. Signed-off-by: Ryder Lee --- .../wireless/mediatek/mt76/mt7615/debugfs.c | 4 +++- .../net/wireless/mediatek/mt76/mt7615/mac.c | 21 ++++++++++--------- .../net/wireless/mediatek/mt76/mt7615/regs.h | 3 ++- 3 files changed, 16 insertions(+), 12 deletions(-) diff --git a/drivers/net/wireless/mediatek/mt76/mt7615/debugfs.c b/drivers/net/wireless/mediatek/mt76/mt7615/debugfs.c index 9fd40d723201..980e7e3cf37e 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7615/debugfs.c +++ b/drivers/net/wireless/mediatek/mt76/mt7615/debugfs.c @@ -145,8 +145,10 @@ mt7615_ampdu_stat_read_phy(struct mt7615_phy *phy, seq_printf(file, "%3d -%3d | ", bound[i], bound[i + 1]); seq_puts(file, "\nCount: "); + + range = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0; for (i = 0; i < ARRAY_SIZE(bound); i++) - seq_printf(file, "%8d | ", dev->mt76.aggr_stats[i]); + seq_printf(file, "%8d | ", dev->mt76.aggr_stats[i + range]); seq_puts(file, "\n"); } diff --git a/drivers/net/wireless/mediatek/mt76/mt7615/mac.c b/drivers/net/wireless/mediatek/mt76/mt7615/mac.c index a27a6d164009..8572973cc4c8 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7615/mac.c +++ b/drivers/net/wireless/mediatek/mt76/mt7615/mac.c @@ -82,8 +82,10 @@ void mt7615_mac_reset_counters(struct mt7615_dev *dev) { int i; - for (i = 0; i < 4; i++) - mt76_rr(dev, MT_TX_AGG_CNT(i)); + for (i = 0; i < 4; i++) { + mt76_rr(dev, MT_TX_AGG_CNT(0, i)); + mt76_rr(dev, MT_TX_AGG_CNT(1, i)); + } memset(dev->mt76.aggr_stats, 0, sizeof(dev->mt76.aggr_stats)); dev->mt76.phy.survey_time = ktime_get_boottime(); @@ -1751,13 +1753,14 @@ mt7615_mac_update_mib_stats(struct mt7615_phy *phy) struct mt7615_dev *dev = phy->dev; struct mib_stats *mib = &phy->mib; bool ext_phy = phy != &dev->phy; - int i; + int i, aggr; memset(mib, 0, sizeof(*mib)); mib->fcs_err_cnt = mt76_get_field(dev, MT_MIB_SDR3(ext_phy), MT_MIB_SDR3_FCS_ERR_MASK); + aggr = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0; for (i = 0; i < 4; i++) { u32 data, val, val2; @@ -1772,6 +1775,11 @@ mt7615_mac_update_mib_stats(struct mt7615_phy *phy) mib->rts_cnt = FIELD_GET(MT_MIB_RTS_COUNT_MASK, val2); mib->rts_retries_cnt = data; } + + val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i)); + + dev->mt76.aggr_stats[aggr++] += val & 0xffff; + dev->mt76.aggr_stats[aggr++] += val >> 16; } } @@ -1779,7 +1787,6 @@ void mt7615_mac_work(struct work_struct *work) { struct mt7615_dev *dev; struct mt7615_phy *ext_phy; - int i, idx; dev = (struct mt7615_dev *)container_of(work, struct mt76_dev, mac_work.work); @@ -1799,12 +1806,6 @@ void mt7615_mac_work(struct work_struct *work) dev->mac_work_count = 0; } - for (i = 0, idx = 0; i < 4; i++) { - u32 val = mt76_rr(dev, MT_TX_AGG_CNT(i)); - - dev->mt76.aggr_stats[idx++] += val & 0xffff; - dev->mt76.aggr_stats[idx++] += val >> 16; - } mutex_unlock(&dev->mt76.mutex); mt76_tx_status_check(&dev->mt76, NULL, false); diff --git a/drivers/net/wireless/mediatek/mt76/mt7615/regs.h b/drivers/net/wireless/mediatek/mt76/mt7615/regs.h index 1e0d95b917e1..d91041613df8 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7615/regs.h +++ b/drivers/net/wireless/mediatek/mt76/mt7615/regs.h @@ -406,7 +406,8 @@ enum mt7615_reg_base { ((n) << 4)) #define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16) -#define MT_TX_AGG_CNT(n) MT_WF_MIB(0xa8 + ((n) << 2)) +#define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(0xa8 + ((_band) << 9) + \ + ((n) << 2)) #define MT_DMA_SHDL(ofs) (dev->reg_map[MT_DMA_SHDL_BASE] + (ofs))