| Message ID | 20200401184219.14911-1-andrzej.jakowski@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v1] nvme: indicate CMB support through controller capabilities register | expand |
On Apr 1 11:42, Andrzej Jakowski wrote: > This patch sets CMBS bit in controller capabilities register when user > configures NVMe driver with CMB support, so capabilites are correctly reported > to guest OS. > > Signed-off-by: Andrzej Jakowski <andrzej.jakowski@linux.intel.com> > --- > hw/block/nvme.c | 2 ++ > include/block/nvme.h | 4 ++++ > 2 files changed, 6 insertions(+) > > diff --git a/hw/block/nvme.c b/hw/block/nvme.c > index d28335cbf3..986803398f 100644 > --- a/hw/block/nvme.c > +++ b/hw/block/nvme.c > @@ -1393,6 +1393,8 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp) > n->bar.intmc = n->bar.intms = 0; > > if (n->cmb_size_mb) { > + /* Contoller capabilities */ > + NVME_CAP_SET_CMBS(n->bar.cap, 1); > > NVME_CMBLOC_SET_BIR(n->bar.cmbloc, 2); > NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0); > diff --git a/include/block/nvme.h b/include/block/nvme.h > index 8fb941c653..561891b140 100644 > --- a/include/block/nvme.h > +++ b/include/block/nvme.h > @@ -27,6 +27,7 @@ enum NvmeCapShift { > CAP_CSS_SHIFT = 37, > CAP_MPSMIN_SHIFT = 48, > CAP_MPSMAX_SHIFT = 52, > + CAP_CMB_SHIFT = 57, > }; > > enum NvmeCapMask { > @@ -39,6 +40,7 @@ enum NvmeCapMask { > CAP_CSS_MASK = 0xff, > CAP_MPSMIN_MASK = 0xf, > CAP_MPSMAX_MASK = 0xf, > + CAP_CMB_MASK = 0x1, > }; > > #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) > @@ -69,6 +71,8 @@ enum NvmeCapMask { > << CAP_MPSMIN_SHIFT) > #define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\ > << CAP_MPSMAX_SHIFT) > +#define NVME_CAP_SET_CMBS(cap, val) (cap |= (uint64_t)(val & CAP_CMB_MASK)\ > + << CAP_CMB_SHIFT) > > enum NvmeCcShift { > CC_EN_SHIFT = 0, > -- > 2.21.1 > Looks good. Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
diff --git a/hw/block/nvme.c b/hw/block/nvme.c index d28335cbf3..986803398f 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1393,6 +1393,8 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp) n->bar.intmc = n->bar.intms = 0; if (n->cmb_size_mb) { + /* Contoller capabilities */ + NVME_CAP_SET_CMBS(n->bar.cap, 1); NVME_CMBLOC_SET_BIR(n->bar.cmbloc, 2); NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0); diff --git a/include/block/nvme.h b/include/block/nvme.h index 8fb941c653..561891b140 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -27,6 +27,7 @@ enum NvmeCapShift { CAP_CSS_SHIFT = 37, CAP_MPSMIN_SHIFT = 48, CAP_MPSMAX_SHIFT = 52, + CAP_CMB_SHIFT = 57, }; enum NvmeCapMask { @@ -39,6 +40,7 @@ enum NvmeCapMask { CAP_CSS_MASK = 0xff, CAP_MPSMIN_MASK = 0xf, CAP_MPSMAX_MASK = 0xf, + CAP_CMB_MASK = 0x1, }; #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) @@ -69,6 +71,8 @@ enum NvmeCapMask { << CAP_MPSMIN_SHIFT) #define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\ << CAP_MPSMAX_SHIFT) +#define NVME_CAP_SET_CMBS(cap, val) (cap |= (uint64_t)(val & CAP_CMB_MASK)\ + << CAP_CMB_SHIFT) enum NvmeCcShift { CC_EN_SHIFT = 0,
This patch sets CMBS bit in controller capabilities register when user configures NVMe driver with CMB support, so capabilites are correctly reported to guest OS. Signed-off-by: Andrzej Jakowski <andrzej.jakowski@linux.intel.com> --- hw/block/nvme.c | 2 ++ include/block/nvme.h | 4 ++++ 2 files changed, 6 insertions(+)