| Message ID | 1341240671-5843-10-git-send-email-eugeni.dodonov@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, 2 Jul 2012 11:51:10 -0300 Eugeni Dodonov <eugeni.dodonov@intel.com> wrote: > For Haswell, on some of the early hardware revisions, it is possible to > run into issues when RC6 state is enabled and when pipes change state. > > v2: add comment saying that this is for early revisions only. > > v3: beautify as suggested by Daniel Vetter. > > Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Acked-by: Ben Widawsky <ben@bwidawsk.net> > --- > drivers/gpu/drm/i915/i915_reg.h | 5 +++++ > drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++ > 2 files changed, 15 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 9d5bf06..793a172 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4516,4 +4516,9 @@ > #define SFUSE_STRAP_DDIC_DETECTED (1<<1) > #define SFUSE_STRAP_DDID_DETECTED (1<<0) > > +#define WM_DBG 0x45280 > +#define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0) > +#define WM_DBG_DISALLOW_MAXFIFO (1<<1) > +#define WM_DBG_DISALLOW_SPRITE (1<<2) > + > #endif /* _I915_REG_H_ */ > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index f54196f..604f9bf 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3465,6 +3465,16 @@ static void haswell_init_clock_gating(struct drm_device *dev) > /* WaDisable4x2SubspanOptimization */ > I915_WRITE(CACHE_MODE_1, > _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); > + > + /* XXX: This is a workaround for early silicon revisions and should be > + * removed later. > + */ > + I915_WRITE(WM_DBG, > + I915_READ(WM_DBG) | > + WM_DBG_DISALLOW_MULTIPLE_LP | > + WM_DBG_DISALLOW_SPRITE | > + WM_DBG_DISALLOW_MAXFIFO); > + > } > > static void ivybridge_init_clock_gating(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9d5bf06..793a172 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4516,4 +4516,9 @@ #define SFUSE_STRAP_DDIC_DETECTED (1<<1) #define SFUSE_STRAP_DDID_DETECTED (1<<0) +#define WM_DBG 0x45280 +#define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0) +#define WM_DBG_DISALLOW_MAXFIFO (1<<1) +#define WM_DBG_DISALLOW_SPRITE (1<<2) + #endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f54196f..604f9bf 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3465,6 +3465,16 @@ static void haswell_init_clock_gating(struct drm_device *dev) /* WaDisable4x2SubspanOptimization */ I915_WRITE(CACHE_MODE_1, _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); + + /* XXX: This is a workaround for early silicon revisions and should be + * removed later. + */ + I915_WRITE(WM_DBG, + I915_READ(WM_DBG) | + WM_DBG_DISALLOW_MULTIPLE_LP | + WM_DBG_DISALLOW_SPRITE | + WM_DBG_DISALLOW_MAXFIFO); + } static void ivybridge_init_clock_gating(struct drm_device *dev)
For Haswell, on some of the early hardware revisions, it is possible to run into issues when RC6 state is enabled and when pipes change state. v2: add comment saying that this is for early revisions only. v3: beautify as suggested by Daniel Vetter. Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 5 +++++ drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++ 2 files changed, 15 insertions(+)