@@ -1684,8 +1684,25 @@ void intel_rps_init(struct intel_rps *rps)
if (INTEL_GEN(i915) <= 7)
rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
- if (INTEL_GEN(i915) >= 8 && INTEL_GEN(i915) < 11)
- rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
+ if (INTEL_GEN(i915) >= 8) {
+ /*
+ * The PMINTRMSK is not replicated on the GuC side, even on
+ * gen11+ where GuC has additional control over its own
+ * interrupts. The GuC does update the register during load to
+ * unmask the ARAT interrupt, but we still need to make sure our
+ * handler doesn't overwrite the setting.
+ * On Gen11+ the ARAT interrupt is sent only to the GuC, while
+ * on older gens we need to explicitly redirect it using the
+ * GEN8_PMINTR_REDIRECT_TO_GUC bit; this bit is on the same
+ * register, but it is not a mask and therefore we need to make
+ * sure we leave it to one after GuC sets it (i.e. it is not a
+ * mbz bit when GuC is enabled).
+ */
+ if (intel_uc_uses_guc(&rps_to_gt(rps)->uc))
+ rps->pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK;
+ else if (INTEL_GEN(i915) < 11)
+ rps->pm_intrmsk_mbz |= GEN8_PMINTR_REDIRECT_TO_GUC;
+ }
}
u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
@@ -9010,7 +9010,7 @@ enum {
#define VLV_RCEDATA _MMIO(0xA0BC)
#define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)
#define GEN6_PMINTRMSK _MMIO(0xA168)
-#define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31)
+#define GEN8_PMINTR_REDIRECT_TO_GUC (1 << 31)
#define ARAT_EXPIRED_INTRMSK (1 << 9)
#define GEN8_MISC_CTRL0 _MMIO(0xA180)
#define VLV_PWRDWNUPCTL _MMIO(0xA294)
This is required for GuC to be able to handle timeouts. This is mainly needed when using GuC submission, but there is no rule saying this won't be used to handle HuC-related actions so turn it always on when using the GuC. The routing bit name has also been renamed to indicate what it actually does, i.e. setting the bit enables the routing to GuC (the bit name was flipped because we use it in a mbz mask, in which we set the bits we don't want to be set in the register). Note that the ARAT interrupt used to be enabled in GuC submission mode, but was then removed in commit 1cdc2330e8d3 ("drm/i915/guc: Properly capture & release GuC interrupts on Gen11+"). While it is true that, as stated in that patch, the host and the GuC have independent masks for the interrupts, the PM interrupts still need to be additionally globally unmasked in the PMINTRMSK register. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Matthew Brost <matthew.brost@intel.com> --- drivers/gpu/drm/i915/gt/intel_rps.c | 21 +++++++++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 20 insertions(+), 3 deletions(-)