[v4,1/4] drm/i915: Power well id for ICL PG3
diff mbox series

Message ID 20200409060646.30817-2-anshuman.gupta@intel.com
State New
Headers show
Series
  • i915 lpsp support for lpsp igt
Related show

Commit Message

Anshuman Gupta April 9, 2020, 6:06 a.m. UTC
Gen11 onwards PG3 is contains functions for pipe B,
external displays, and VGA. It make sense to add
a power well id with name ICL_DISP_PW_3 rather then
TGL_DISP_PW_3, Also PG3 power well id requires to
know if lpsp is enabled.

Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++---
 drivers/gpu/drm/i915/display/intel_display_power.h | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

Comments

Manna, Animesh April 14, 2020, 2:22 p.m. UTC | #1
On 09-04-2020 11:36, Anshuman Gupta wrote:
> Gen11 onwards PG3 is contains functions for pipe B,
> external displays, and VGA. It make sense to add
> a power well id with name ICL_DISP_PW_3 rather then
> TGL_DISP_PW_3, Also PG3 power well id requires to
> know if lpsp is enabled.
>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>

Looks good to me.
Reviewed-by: Animesh Manna <animesh.manna@intel.com>

> ---
>   drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++---
>   drivers/gpu/drm/i915/display/intel_display_power.h | 2 +-
>   2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 433e5a81dd4d..3672c00be94a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -943,7 +943,7 @@ static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
>   
>   	/* Power wells at this level and above must be disabled for DC5 entry */
>   	if (INTEL_GEN(dev_priv) >= 12)
> -		high_pg = TGL_DISP_PW_3;
> +		high_pg = ICL_DISP_PW_3;
>   	else
>   		high_pg = SKL_DISP_PW_2;
>   
> @@ -3571,7 +3571,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
>   		.name = "power well 3",
>   		.domains = ICL_PW_3_POWER_DOMAINS,
>   		.ops = &hsw_power_well_ops,
> -		.id = DISP_PW_ID_NONE,
> +		.id = ICL_DISP_PW_3,
>   		{
>   			.hsw.regs = &hsw_power_well_regs,
>   			.hsw.idx = ICL_PW_CTL_IDX_PW_3,
> @@ -3949,7 +3949,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
>   		.name = "power well 3",
>   		.domains = TGL_PW_3_POWER_DOMAINS,
>   		.ops = &hsw_power_well_ops,
> -		.id = TGL_DISP_PW_3,
> +		.id = ICL_DISP_PW_3,
>   		{
>   			.hsw.regs = &hsw_power_well_regs,
>   			.hsw.idx = ICL_PW_CTL_IDX_PW_3,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index da64a5edae7a..56cbae6327b7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -100,7 +100,7 @@ enum i915_power_well_id {
>   	SKL_DISP_PW_MISC_IO,
>   	SKL_DISP_PW_1,
>   	SKL_DISP_PW_2,
> -	TGL_DISP_PW_3,
> +	ICL_DISP_PW_3,
>   	SKL_DISP_DC_OFF,
>   };
>

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 433e5a81dd4d..3672c00be94a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -943,7 +943,7 @@  static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 
 	/* Power wells at this level and above must be disabled for DC5 entry */
 	if (INTEL_GEN(dev_priv) >= 12)
-		high_pg = TGL_DISP_PW_3;
+		high_pg = ICL_DISP_PW_3;
 	else
 		high_pg = SKL_DISP_PW_2;
 
@@ -3571,7 +3571,7 @@  static const struct i915_power_well_desc icl_power_wells[] = {
 		.name = "power well 3",
 		.domains = ICL_PW_3_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = DISP_PW_ID_NONE,
+		.id = ICL_DISP_PW_3,
 		{
 			.hsw.regs = &hsw_power_well_regs,
 			.hsw.idx = ICL_PW_CTL_IDX_PW_3,
@@ -3949,7 +3949,7 @@  static const struct i915_power_well_desc tgl_power_wells[] = {
 		.name = "power well 3",
 		.domains = TGL_PW_3_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = TGL_DISP_PW_3,
+		.id = ICL_DISP_PW_3,
 		{
 			.hsw.regs = &hsw_power_well_regs,
 			.hsw.idx = ICL_PW_CTL_IDX_PW_3,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index da64a5edae7a..56cbae6327b7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -100,7 +100,7 @@  enum i915_power_well_id {
 	SKL_DISP_PW_MISC_IO,
 	SKL_DISP_PW_1,
 	SKL_DISP_PW_2,
-	TGL_DISP_PW_3,
+	ICL_DISP_PW_3,
 	SKL_DISP_DC_OFF,
 };