diff mbox series

[v22,06/13] drm/i915: Add pre/post plane updates for SAGV

Message ID 20200409154730.18568-7-stanislav.lisovskiy@intel.com (mailing list archive)
State New, archived
Headers show
Series SAGV support for Gen12+ | expand

Commit Message

Lisovskiy, Stanislav April 9, 2020, 3:47 p.m. UTC 
Lets have a unified way to handle SAGV changes,
espoecially considering the upcoming Gen12 changes.

Current "standard" way of doing this in commit_tail
is pre/post plane updates, when everything which
has to be forbidden and not supported in new config
has to be restricted before update and relaxed after
plane update.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 13 ++++---------
 drivers/gpu/drm/i915/intel_pm.c              | 20 ++++++++++++++++++++
 drivers/gpu/drm/i915/intel_pm.h              |  2 ++
 3 files changed, 26 insertions(+), 9 deletions(-)

Comments

Ville Syrjälä April 14, 2020, 5:42 p.m. UTC | #1 
On Thu, Apr 09, 2020 at 06:47:23PM +0300, Stanislav Lisovskiy wrote:
> Lets have a unified way to handle SAGV changes,
> espoecially considering the upcoming Gen12 changes.
> 
> Current "standard" way of doing this in commit_tail
> is pre/post plane updates, when everything which
> has to be forbidden and not supported in new config
> has to be restricted before update and relaxed after
> plane update.
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 13 ++++---------
>  drivers/gpu/drm/i915/intel_pm.c              | 20 ++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_pm.h              |  2 ++
>  3 files changed, 26 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 70ec301fe6e3..ac7f600c84ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15349,12 +15349,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  
>  		intel_set_cdclk_pre_plane_update(state);
>  
> -		/*
> -		 * SKL workaround: bspec recommends we disable the SAGV when we
> -		 * have more then one pipe enabled
> -		 */
> -		if (!intel_can_enable_sagv(state))
> -			intel_disable_sagv(dev_priv);
> +		intel_sagv_pre_plane_update(state);
>  
>  		intel_modeset_verify_disabled(dev_priv, state);
>  	}
> @@ -15451,11 +15446,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  	intel_check_cpu_fifo_underruns(dev_priv);
>  	intel_check_pch_fifo_underruns(dev_priv);
>  
> -	if (state->modeset)
> +	if (state->modeset) {
>  		intel_verify_planes(state);
>  
> -	if (state->modeset && intel_can_enable_sagv(state))
> -		intel_enable_sagv(dev_priv);
> +		intel_sagv_post_plane_update(state);
> +	}
>  
>  	drm_atomic_helper_commit_hw_done(&state->base);
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 41af69ad3edc..d1df288396d8 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3757,6 +3757,26 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
>  	return 0;
>  }
>  
> +void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +
> +	if (!intel_can_enable_sagv(state)) {
> +		intel_disable_sagv(dev_priv);
> +		return;
> +	}
> +}
> +
> +void intel_sagv_post_plane_update(struct intel_atomic_state *state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +
> +	if (intel_can_enable_sagv(state)) {
> +		intel_enable_sagv(dev_priv);
> +		return;

Pointless returns. With those removed

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +	}
> +}
> +
>  static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index d60a85421c5a..9a6036ab0f90 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -44,6 +44,8 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
>  bool intel_can_enable_sagv(struct intel_atomic_state *state);
>  int intel_enable_sagv(struct drm_i915_private *dev_priv);
>  int intel_disable_sagv(struct drm_i915_private *dev_priv);
> +void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
> +void intel_sagv_post_plane_update(struct intel_atomic_state *state);
>  bool skl_wm_level_equals(const struct skl_wm_level *l1,
>  			 const struct skl_wm_level *l2);
>  bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
> -- 
> 2.24.1.485.gad05a3d8e5
Lisovskiy, Stanislav April 15, 2020, 8:04 a.m. UTC | #2 
On Tue, Apr 14, 2020 at 08:42:25PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 09, 2020 at 06:47:23PM +0300, Stanislav Lisovskiy wrote:
> > Lets have a unified way to handle SAGV changes,
> > espoecially considering the upcoming Gen12 changes.
> > 
> > Current "standard" way of doing this in commit_tail
> > is pre/post plane updates, when everything which
> > has to be forbidden and not supported in new config
> > has to be restricted before update and relaxed after
> > plane update.
> > 
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 13 ++++---------
> >  drivers/gpu/drm/i915/intel_pm.c              | 20 ++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_pm.h              |  2 ++
> >  3 files changed, 26 insertions(+), 9 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 70ec301fe6e3..ac7f600c84ca 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -15349,12 +15349,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> >  
> >  		intel_set_cdclk_pre_plane_update(state);
> >  
> > -		/*
> > -		 * SKL workaround: bspec recommends we disable the SAGV when we
> > -		 * have more then one pipe enabled
> > -		 */
> > -		if (!intel_can_enable_sagv(state))
> > -			intel_disable_sagv(dev_priv);
> > +		intel_sagv_pre_plane_update(state);
> >  
> >  		intel_modeset_verify_disabled(dev_priv, state);
> >  	}
> > @@ -15451,11 +15446,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> >  	intel_check_cpu_fifo_underruns(dev_priv);
> >  	intel_check_pch_fifo_underruns(dev_priv);
> >  
> > -	if (state->modeset)
> > +	if (state->modeset) {
> >  		intel_verify_planes(state);
> >  
> > -	if (state->modeset && intel_can_enable_sagv(state))
> > -		intel_enable_sagv(dev_priv);
> > +		intel_sagv_post_plane_update(state);
> > +	}
> >  
> >  	drm_atomic_helper_commit_hw_done(&state->base);
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 41af69ad3edc..d1df288396d8 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3757,6 +3757,26 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> >  	return 0;
> >  }
> >  
> > +void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > +
> > +	if (!intel_can_enable_sagv(state)) {
> > +		intel_disable_sagv(dev_priv);
> > +		return;
> > +	}
> > +}
> > +
> > +void intel_sagv_post_plane_update(struct intel_atomic_state *state)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > +
> > +	if (intel_can_enable_sagv(state)) {
> > +		intel_enable_sagv(dev_priv);
> > +		return;
> 
> Pointless returns. With those removed

Agree, my vision was way to blurry after reshuffling.

> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> > +	}
> > +}
> > +
> >  static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> > index d60a85421c5a..9a6036ab0f90 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.h
> > +++ b/drivers/gpu/drm/i915/intel_pm.h
> > @@ -44,6 +44,8 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> >  bool intel_can_enable_sagv(struct intel_atomic_state *state);
> >  int intel_enable_sagv(struct drm_i915_private *dev_priv);
> >  int intel_disable_sagv(struct drm_i915_private *dev_priv);
> > +void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
> > +void intel_sagv_post_plane_update(struct intel_atomic_state *state);
> >  bool skl_wm_level_equals(const struct skl_wm_level *l1,
> >  			 const struct skl_wm_level *l2);
> >  bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
> > -- 
> > 2.24.1.485.gad05a3d8e5
> 
> -- 
> Ville Syrjälä
> Intel
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 70ec301fe6e3..ac7f600c84ca 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15349,12 +15349,7 @@  static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 
 		intel_set_cdclk_pre_plane_update(state);
 
-		/*
-		 * SKL workaround: bspec recommends we disable the SAGV when we
-		 * have more then one pipe enabled
-		 */
-		if (!intel_can_enable_sagv(state))
-			intel_disable_sagv(dev_priv);
+		intel_sagv_pre_plane_update(state);
 
 		intel_modeset_verify_disabled(dev_priv, state);
 	}
@@ -15451,11 +15446,11 @@  static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	intel_check_cpu_fifo_underruns(dev_priv);
 	intel_check_pch_fifo_underruns(dev_priv);
 
-	if (state->modeset)
+	if (state->modeset) {
 		intel_verify_planes(state);
 
-	if (state->modeset && intel_can_enable_sagv(state))
-		intel_enable_sagv(dev_priv);
+		intel_sagv_post_plane_update(state);
+	}
 
 	drm_atomic_helper_commit_hw_done(&state->base);
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 41af69ad3edc..d1df288396d8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3757,6 +3757,26 @@  intel_disable_sagv(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
+void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+
+	if (!intel_can_enable_sagv(state)) {
+		intel_disable_sagv(dev_priv);
+		return;
+	}
+}
+
+void intel_sagv_post_plane_update(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+
+	if (intel_can_enable_sagv(state)) {
+		intel_enable_sagv(dev_priv);
+		return;
+	}
+}
+
 static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index d60a85421c5a..9a6036ab0f90 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -44,6 +44,8 @@  void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
 bool intel_can_enable_sagv(struct intel_atomic_state *state);
 int intel_enable_sagv(struct drm_i915_private *dev_priv);
 int intel_disable_sagv(struct drm_i915_private *dev_priv);
+void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
+void intel_sagv_post_plane_update(struct intel_atomic_state *state);
 bool skl_wm_level_equals(const struct skl_wm_level *l1,
 			 const struct skl_wm_level *l2);
 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,