| Message ID | 1586870668-32630-2-git-send-email-peng.fan@nxp.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 6895681132ec9d0dda9e95a9ddde3ba59720c1d6 |
| Headers | show |
| Series | [1/2] dt-bindings: mailbox: imx-mu: correct example | expand |
On Tue, Apr 14, 2020 at 09:24:28PM +0800, peng.fan@nxp.com wrote: > From: Peng Fan <peng.fan@nxp.com> > > With mailbox driver support i.MX8 SCU MU channel, we could > use it to avoid trigger interrupts for each TR/RR registers > in one MU, instead, only one RX interrupt for a recv and > one TX interrupt for a send. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> > --- > > Note: > This patch needs https://patchwork.kernel.org/patch/11446659/ > The other three patches in the patchset has been in linux-next > > arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 18 ++++++------------ > 1 file changed, 6 insertions(+), 12 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > index e8ffb7590656..d1c3c98e4b39 100644 > --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > @@ -141,17 +141,11 @@ > > scu { > compatible = "fsl,imx-scu"; > - mbox-names = "tx0", "tx1", "tx2", "tx3", > - "rx0", "rx1", "rx2", "rx3", > + mbox-names = "tx0", > + "rx0", > "gip3"; > mboxes = <&lsio_mu1 0 0 > - &lsio_mu1 0 1 > - &lsio_mu1 0 2 > - &lsio_mu1 0 3 > &lsio_mu1 1 0 > - &lsio_mu1 1 1 > - &lsio_mu1 1 2 > - &lsio_mu1 1 3 > &lsio_mu1 3 3>; > > clk: clock-controller { > @@ -548,14 +542,14 @@ > }; > > lsio_mu1: mailbox@5d1c0000 { > - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; > + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; > reg = <0x5d1c0000 0x10000>; > interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; > #mbox-cells = <2>; > }; > > lsio_mu2: mailbox@5d1d0000 { > - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; > + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; > reg = <0x5d1d0000 0x10000>; > interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; > #mbox-cells = <2>; > @@ -563,7 +557,7 @@ > }; > > lsio_mu3: mailbox@5d1e0000 { > - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; > + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; > reg = <0x5d1e0000 0x10000>; > interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; > #mbox-cells = <2>; > @@ -571,7 +565,7 @@ > }; > > lsio_mu4: mailbox@5d1f0000 { > - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; > + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; > reg = <0x5d1f0000 0x10000>; > interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; > #mbox-cells = <2>; > -- > 2.16.4 > > >
On Tue, Apr 14, 2020 at 09:24:28PM +0800, peng.fan@nxp.com wrote: > From: Peng Fan <peng.fan@nxp.com> > > With mailbox driver support i.MX8 SCU MU channel, we could > use it to avoid trigger interrupts for each TR/RR registers > in one MU, instead, only one RX interrupt for a recv and > one TX interrupt for a send. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> Applied, thanks.
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index e8ffb7590656..d1c3c98e4b39 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -141,17 +141,11 @@ scu { compatible = "fsl,imx-scu"; - mbox-names = "tx0", "tx1", "tx2", "tx3", - "rx0", "rx1", "rx2", "rx3", + mbox-names = "tx0", + "rx0", "gip3"; mboxes = <&lsio_mu1 0 0 - &lsio_mu1 0 1 - &lsio_mu1 0 2 - &lsio_mu1 0 3 &lsio_mu1 1 0 - &lsio_mu1 1 1 - &lsio_mu1 1 2 - &lsio_mu1 1 3 &lsio_mu1 3 3>; clk: clock-controller { @@ -548,14 +542,14 @@ }; lsio_mu1: mailbox@5d1c0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; reg = <0x5d1c0000 0x10000>; interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; #mbox-cells = <2>; }; lsio_mu2: mailbox@5d1d0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; reg = <0x5d1d0000 0x10000>; interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; #mbox-cells = <2>; @@ -563,7 +557,7 @@ }; lsio_mu3: mailbox@5d1e0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; reg = <0x5d1e0000 0x10000>; interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; #mbox-cells = <2>; @@ -571,7 +565,7 @@ }; lsio_mu4: mailbox@5d1f0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; reg = <0x5d1f0000 0x10000>; interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; #mbox-cells = <2>;