@@ -79,7 +79,7 @@ on the Qualcomm Hexagon core.
"snoc_axi", "mnoc_axi", "qdss"
qcom,sc7180-mss-pil:
must be "iface", "bus", "xo", "snoc_axi", "mnoc_axi",
- "mss_crypto", "mss_nav", "nav"
+ "nav"
qcom,sdm845-mss-pil:
must be "iface", "bus", "mem", "xo", "gpll0_mss",
"snoc_axi", "mnoc_axi", "prng"
@@ -173,16 +173,12 @@ For the compatible string below the following supplies are required:
For the compatible strings below the following phandle references are required:
"qcom,sc7180-mss-pil"
-- qcom,halt-nav-regs:
+- qcom,spare-regs:
Usage: required
Value type: <prop-encoded-array>
- Definition: reference to a list of 2 phandles with one offset each for
- the modem sub-system running on SC7180 SoC. The first
- phandle reference is to the mss clock node followed by the
- offset within register space for nav halt register. The
- second phandle reference is to a syscon representing TCSR
- followed by the offset within syscon for conn_box_spare0
- register.
+ Definition: a phandle reference to a syscon representing TCSR followed
+ by the offset within syscon for conn_box_spare0 register
+ used by the modem sub-system running on SC7180 SoC.
= SUBNODES:
The Hexagon node must contain two subnodes, named "mba" and "mpss" representing
7C retail devices using MSA based boot will result in a fuse combination which will prevent accesses to MSS PERPH register space where the mpss clocks and halt-nav reside. However accesses to conn_box_spare0 in TCSR register space is still permitted so rename the binding appropriately to qcom,spare-regs and drop all accesses to the MPSS PERPH register space. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> --- .../devicetree/bindings/remoteproc/qcom,q6v5.txt | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-)