[v2] drm/i915/tgl: Wa_14011059788
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Message ID 20200415193535.14597-1-matthew.s.atwood@intel.com
State New
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  • [v2] drm/i915/tgl: Wa_14011059788
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Commit Message

Matt Atwood April 15, 2020, 7:35 p.m. UTC
Reflect recent Bspec changes

v2: fix whitespace, typo

Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Radhakrishna Sripada April 28, 2020, 3:07 p.m. UTC | #1
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Matt
> Atwood
> Sent: Wednesday, April 15, 2020 12:36 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2] drm/i915/tgl: Wa_14011059788
> 
> Reflect recent Bspec changes
> 
> v2: fix whitespace, typo
> 
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Looks good to me.
Reviewed-by: Radhakrishna Sripada <Radhakrishna.sripada@intel.com>

- RK
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b632b6bb9c3e..3d12a0617c84 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6854,6 +6854,10 @@ static void tgl_init_clock_gating(struct
> drm_i915_private *dev_priv)
>  	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
>  		I915_WRITE(GEN9_CLKGATE_DIS_3,
> I915_READ(GEN9_CLKGATE_DIS_3) |
>  			   TGL_VRH_GATING_DIS);
> +
> +	/* Wa_14011059788:tgl */
> +	intel_uncore_rmw(&dev_priv->uncore,
> GEN10_DFR_RATIO_EN_AND_CHICKEN,
> +			 0, DFR_DISABLE);
>  }
> 
>  static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
> --
> 2.21.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Vivi, Rodrigo April 28, 2020, 6:50 p.m. UTC | #2
On Tue, Apr 28, 2020 at 03:07:03PM +0000, Sripada, Radhakrishna wrote:
> 
> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Matt
> > Atwood
> > Sent: Wednesday, April 15, 2020 12:36 PM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [Intel-gfx] [PATCH v2] drm/i915/tgl: Wa_14011059788
> > 
> > Reflect recent Bspec changes
> > 
> > v2: fix whitespace, typo
> > 
> > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> Looks good to me.
> Reviewed-by: Radhakrishna Sripada <Radhakrishna.sripada@intel.com>

pushed to dinq.
Thanks for the patch and review.

> 
> - RK
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index b632b6bb9c3e..3d12a0617c84 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -6854,6 +6854,10 @@ static void tgl_init_clock_gating(struct
> > drm_i915_private *dev_priv)
> >  	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
> >  		I915_WRITE(GEN9_CLKGATE_DIS_3,
> > I915_READ(GEN9_CLKGATE_DIS_3) |
> >  			   TGL_VRH_GATING_DIS);
> > +
> > +	/* Wa_14011059788:tgl */
> > +	intel_uncore_rmw(&dev_priv->uncore,
> > GEN10_DFR_RATIO_EN_AND_CHICKEN,
> > +			 0, DFR_DISABLE);
> >  }
> > 
> >  static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
> > --
> > 2.21.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b632b6bb9c3e..3d12a0617c84 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6854,6 +6854,10 @@  static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
 	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
 		I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
 			   TGL_VRH_GATING_DIS);
+
+	/* Wa_14011059788:tgl */
+	intel_uncore_rmw(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN,
+			 0, DFR_DISABLE);
 }
 
 static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)