Message ID | 20200420200610.31798-4-ville.syrjala@linux.intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [1/4] drm/i915: Introduce .set_link_train() vfunc | expand |
On Mon, 2020-04-20 at 23:06 +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Split some overly long lines. Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index ad172a38ea38..1f3df8396d3a 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -1261,7 +1261,10 @@ void hsw_fdi_link_train(struct intel_encoder > *encoder, > for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) > { > /* Configure DP_TP_CTL with auto-training */ > intel_de_write(dev_priv, DP_TP_CTL(PORT_E), > - DP_TP_CTL_FDI_AUTOTRAIN | > DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1 | > DP_TP_CTL_ENABLE); > + DP_TP_CTL_FDI_AUTOTRAIN | > + DP_TP_CTL_ENHANCED_FRAME_ENABLE | > + DP_TP_CTL_LINK_TRAIN_PAT1 | > + DP_TP_CTL_ENABLE); > > /* Configure and enable DDI_BUF_CTL for DDI E with next > voltage. > * DDI E does not support port reversal, the > functionality is > @@ -1337,7 +1340,10 @@ void hsw_fdi_link_train(struct intel_encoder > *encoder, > > /* Enable normal pixel sending for FDI */ > intel_de_write(dev_priv, DP_TP_CTL(PORT_E), > - DP_TP_CTL_FDI_AUTOTRAIN | > DP_TP_CTL_LINK_TRAIN_NORMAL | DP_TP_CTL_ENHANCED_FRAME_ENABLE | > DP_TP_CTL_ENABLE); > + DP_TP_CTL_FDI_AUTOTRAIN | > + DP_TP_CTL_LINK_TRAIN_NORMAL | > + DP_TP_CTL_ENHANCED_FRAME_ENABLE | > + DP_TP_CTL_ENABLE); > } > > static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ad172a38ea38..1f3df8396d3a 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1261,7 +1261,10 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { /* Configure DP_TP_CTL with auto-training */ intel_de_write(dev_priv, DP_TP_CTL(PORT_E), - DP_TP_CTL_FDI_AUTOTRAIN | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_ENABLE); + DP_TP_CTL_FDI_AUTOTRAIN | + DP_TP_CTL_ENHANCED_FRAME_ENABLE | + DP_TP_CTL_LINK_TRAIN_PAT1 | + DP_TP_CTL_ENABLE); /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. * DDI E does not support port reversal, the functionality is @@ -1337,7 +1340,10 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, /* Enable normal pixel sending for FDI */ intel_de_write(dev_priv, DP_TP_CTL(PORT_E), - DP_TP_CTL_FDI_AUTOTRAIN | DP_TP_CTL_LINK_TRAIN_NORMAL | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_ENABLE); + DP_TP_CTL_FDI_AUTOTRAIN | + DP_TP_CTL_LINK_TRAIN_NORMAL | + DP_TP_CTL_ENHANCED_FRAME_ENABLE | + DP_TP_CTL_ENABLE); } static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)