| Message ID | 20200428172433.48830-3-broonie@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: Make NOP handling a whitelist | expand |
On Tue, Apr 28, 2020 at 06:24:32PM +0100, Mark Brown wrote: > Add constants for decoding the various PAC and BTI instructions defined > in the HINT space. Since we are now decoding both the op2 and CRm fields > rename the enum as well; this is compatible with what the existing users > are doing. > > Signed-off-by: Mark Brown <broonie@kernel.org> > Acked-by: Catalin Marinas <catalin.marinas@arm.com> > --- > arch/arm64/include/asm/insn.h | 22 ++++++++++++++++++++-- > arch/arm64/kernel/insn.c | 2 +- > 2 files changed, 21 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h > index bb313dde58a4..e5a87f98a548 100644 > --- a/arch/arm64/include/asm/insn.h > +++ b/arch/arm64/include/asm/insn.h > @@ -39,13 +39,31 @@ enum aarch64_insn_encoding_class { > * system instructions */ > }; > > -enum aarch64_insn_hint_op { > +enum aarch64_insn_hint_cr_op { > AARCH64_INSN_HINT_NOP = 0x0 << 5, > AARCH64_INSN_HINT_YIELD = 0x1 << 5, > AARCH64_INSN_HINT_WFE = 0x2 << 5, > AARCH64_INSN_HINT_WFI = 0x3 << 5, > AARCH64_INSN_HINT_SEV = 0x4 << 5, > AARCH64_INSN_HINT_SEVL = 0x5 << 5, > + > + AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5, > + AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5, > + AARCH64_INSN_HINT_AUTIA_1716 = 0x0B << 5, > + AARCH64_INSN_HINT_AUTIB_1716 = 0x0C << 5, These still look wrong to me. > + AARCH64_INSN_HINT_PACIAZ = 0x18 << 5, > + AARCH64_INSN_HINT_PACIASP = 0x19 << 5, > + AARCH64_INSN_HINT_PACIBZ = 0x1A << 5, > + AARCH64_INSN_HINT_PACIBSP = 0x1B << 5, > + AARCH64_INSN_HINT_AUTIAZ = 0x1C << 5, > + AARCH64_INSN_HINT_AUTIASP = 0x1D << 5, This one is typo'd in the Arm ARM as AUTHASP. Seems nobody can get this stuff right! > + AARCH64_INSN_HINT_AUTIBZ = 0x1E << 5, > + AARCH64_INSN_HINT_AUTIBSP = 0x1F << 5, > + > + AARCH64_INSN_HINT_BTI = 0x20 << 5, > + AARCH64_INSN_HINT_BTIC = 0x22 << 5, > + AARCH64_INSN_HINT_BTIJ = 0x24 << 5, > + AARCH64_INSN_HINT_BTIJC = 0x2C << 5, This looks wrong as well. Will
On Thu, Apr 30, 2020 at 05:07:30PM +0100, Will Deacon wrote: > On Tue, Apr 28, 2020 at 06:24:32PM +0100, Mark Brown wrote: > > + AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5, > > + AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5, > > + AARCH64_INSN_HINT_AUTIA_1716 = 0x0B << 5, > > + AARCH64_INSN_HINT_AUTIB_1716 = 0x0C << 5, > These still look wrong to me. Ack, I think I must've glazed over after checking PACIA which is right or missed stuff when cut'n'pasting to verify. > > + AARCH64_INSN_HINT_PACIAZ = 0x18 << 5, > > + AARCH64_INSN_HINT_PACIASP = 0x19 << 5, > > + AARCH64_INSN_HINT_PACIBZ = 0x1A << 5, > > + AARCH64_INSN_HINT_PACIBSP = 0x1B << 5, > > + AARCH64_INSN_HINT_AUTIAZ = 0x1C << 5, > > + AARCH64_INSN_HINT_AUTIASP = 0x1D << 5, > This one is typo'd in the Arm ARM as AUTHASP. Seems nobody can get this > stuff right! It seems to have been fixed in the current revision - or at least AUTIASP is there and text search isn't finding any instances of AUTHASP. > > + AARCH64_INSN_HINT_BTI = 0x20 << 5, > > + AARCH64_INSN_HINT_BTIC = 0x22 << 5, > > + AARCH64_INSN_HINT_BTIJ = 0x24 << 5, > > + AARCH64_INSN_HINT_BTIJC = 0x2C << 5, > This looks wrong as well. _JC is wrong, yes.
diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h index bb313dde58a4..e5a87f98a548 100644 --- a/arch/arm64/include/asm/insn.h +++ b/arch/arm64/include/asm/insn.h @@ -39,13 +39,31 @@ enum aarch64_insn_encoding_class { * system instructions */ }; -enum aarch64_insn_hint_op { +enum aarch64_insn_hint_cr_op { AARCH64_INSN_HINT_NOP = 0x0 << 5, AARCH64_INSN_HINT_YIELD = 0x1 << 5, AARCH64_INSN_HINT_WFE = 0x2 << 5, AARCH64_INSN_HINT_WFI = 0x3 << 5, AARCH64_INSN_HINT_SEV = 0x4 << 5, AARCH64_INSN_HINT_SEVL = 0x5 << 5, + + AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5, + AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5, + AARCH64_INSN_HINT_AUTIA_1716 = 0x0B << 5, + AARCH64_INSN_HINT_AUTIB_1716 = 0x0C << 5, + AARCH64_INSN_HINT_PACIAZ = 0x18 << 5, + AARCH64_INSN_HINT_PACIASP = 0x19 << 5, + AARCH64_INSN_HINT_PACIBZ = 0x1A << 5, + AARCH64_INSN_HINT_PACIBSP = 0x1B << 5, + AARCH64_INSN_HINT_AUTIAZ = 0x1C << 5, + AARCH64_INSN_HINT_AUTIASP = 0x1D << 5, + AARCH64_INSN_HINT_AUTIBZ = 0x1E << 5, + AARCH64_INSN_HINT_AUTIBSP = 0x1F << 5, + + AARCH64_INSN_HINT_BTI = 0x20 << 5, + AARCH64_INSN_HINT_BTIC = 0x22 << 5, + AARCH64_INSN_HINT_BTIJ = 0x24 << 5, + AARCH64_INSN_HINT_BTIJC = 0x2C << 5, }; enum aarch64_insn_imm_type { @@ -370,7 +388,7 @@ u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr, enum aarch64_insn_branch_type type); u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr, enum aarch64_insn_condition cond); -u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_op op); +u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op); u32 aarch64_insn_gen_nop(void); u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg, enum aarch64_insn_branch_type type); diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c index 535a3a7a053e..fd77cdd87c47 100644 --- a/arch/arm64/kernel/insn.c +++ b/arch/arm64/kernel/insn.c @@ -570,7 +570,7 @@ u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr, offset >> 2); } -u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_op op) +u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op) { return aarch64_insn_get_hint_value() | op; }