diff mbox series

drm/i915: Update Slylake PCI IDs

Message ID 20200429114048.15227-1-apodtele@gmail.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Update Slylake PCI IDs | expand

Commit Message

Alexei Podtelezhnikov April 29, 2020, 11:40 a.m. UTC
Add three new devices 0x1913, 0x1915, and 0x1917 also known as 
iSKLULTGT15, iSKLULXGT15, and iSKLDTGT15. Reclassify 0x1923, 0x1927, 
and 0x192A according to specifications. Of note, the second to last
digit seems to correspond to GT#.

Signed-off-by: Alexei Podtelezhnikov <apodtele@gmail.com> 
---
 include/drm/i915_pciids.h | 19 +++++++++++--------
 1 file changed, 11 insertions(+), 8 deletions(-)

--
2.26.2

Comments

Alexei Podtelezhnikov April 29, 2020, 11:54 a.m. UTC | #1
On Wed, 29 Apr 2020, Ville Syrjälä <ville.syrjala at linux.intel.com> wrote:
> On Tue, Apr 28, 2020 at 11:27:50PM -0400, Alexei Podtelezhnikov wrote:
>> Add three new devices 0x1513, 0x1515, and 0x1517 also known as
>
> typo 0x15 vs. 0x19
>
>> iSKLULTGT15, iSKLULXGT15, and iSKLDTGT15. Reclassify 0x1923, 0x1927,
>> and 0x192A according to specifications.
>
> I'd make this three separate patches, just in case we have to revert
> some of these in the future. Most worried about the 0x192a case since
> the evidence is rather poor.

I fixed the typo. The absence of 0x192a from the most recent Windows
drivers indicates that it was never printed. The absence of evidence
is the evidence of absence. The second to last digit indicates that it
was planned as GT3. Lastly, making 3 patches for something
non-existent is such an overkill. These are trivial to revert
line-by-line too. Please be considerate to occasional helpers and do
not ask to much of them.

Regards,
Alexei
Chris Wilson April 29, 2020, 1 p.m. UTC | #2
Quoting Alexei Podtelezhnikov (2020-04-29 12:54:20)
> On Wed, 29 Apr 2020, Ville Syrjälä <ville.syrjala at linux.intel.com> wrote:
> > On Tue, Apr 28, 2020 at 11:27:50PM -0400, Alexei Podtelezhnikov wrote:
> >> Add three new devices 0x1513, 0x1515, and 0x1517 also known as
> >
> > typo 0x15 vs. 0x19
> >
> >> iSKLULTGT15, iSKLULXGT15, and iSKLDTGT15. Reclassify 0x1923, 0x1927,
> >> and 0x192A according to specifications.
> >
> > I'd make this three separate patches, just in case we have to revert
> > some of these in the future. Most worried about the 0x192a case since
> > the evidence is rather poor.
> 
> I fixed the typo.

And slyly hide another.
-Chris
Alexei Podtelezhnikov April 29, 2020, 3:29 p.m. UTC | #3
On Wed, Apr 29, 2020 at 7:41 AM Alexei Podtelezhnikov
<apodtele@gmail.com> wrote:
>
> Add three new devices 0x1913, 0x1915, and 0x1917 also known as
> iSKLULTGT15, iSKLULXGT15, and iSKLDTGT15. Reclassify 0x1923, 0x1927,
> and 0x192A according to specifications. Of note, the second to last
> digit seems to correspond to GT#.

Ehh, GT1.5 is topologically closer to GT2 than to GT1. The second lest
significant digit indicates the same. I should move them there and
resubmit the patch...

Now I am suspicious about Haswell 0x0426, which might have been
planned as GT3 with no evidence of actual existence.
diff mbox series

Patch

diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 1d2c1221..c12bce9e 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -331,15 +331,18 @@ 
 	INTEL_VGA_DEVICE(0x22b3, info)
 
 #define INTEL_SKL_ULT_GT1_IDS(info) \
-	INTEL_VGA_DEVICE(0x1906, info) /* ULT GT1 */
+	INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
+	INTEL_VGA_DEVICE(0x1913, info) /* ULT GT1.5 */
 
 #define INTEL_SKL_ULX_GT1_IDS(info) \
-	INTEL_VGA_DEVICE(0x190E, info) /* ULX GT1 */
+	INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
+	INTEL_VGA_DEVICE(0x1915, info) /* ULX GT1.5 */
 
 #define INTEL_SKL_GT1_IDS(info)	\
 	INTEL_SKL_ULT_GT1_IDS(info), \
 	INTEL_SKL_ULX_GT1_IDS(info), \
 	INTEL_VGA_DEVICE(0x1902, info), /* DT  GT1 */ \
+	INTEL_VGA_DEVICE(0x1917, info), /* DT  GT1.5 */ \
 	INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
 	INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
 
@@ -359,21 +362,21 @@ 
 	INTEL_VGA_DEVICE(0x191D, info)  /* WKS GT2 */
 
 #define INTEL_SKL_ULT_GT3_IDS(info) \
-	INTEL_VGA_DEVICE(0x1926, info) /* ULT GT3 */
+	INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
+	INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 28W */ \
+	INTEL_VGA_DEVICE(0x1926, info) /* ULT GT3e */
 
 #define INTEL_SKL_GT3_IDS(info) \
 	INTEL_SKL_ULT_GT3_IDS(info), \
-	INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
-	INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
+	INTEL_VGA_DEVICE(0x192A, info), /* SRV GT3 */ \
 	INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
-	INTEL_VGA_DEVICE(0x192D, info)  /* SRV GT3 */
+	INTEL_VGA_DEVICE(0x192D, info)  /* SRV GT3e */
 
 #define INTEL_SKL_GT4_IDS(info) \
 	INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
 	INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
 	INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
-	INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \
-	INTEL_VGA_DEVICE(0x193A, info)  /* SRV GT4e */
+	INTEL_VGA_DEVICE(0x193A, info)  /* SRV GT4 */
 
 #define INTEL_SKL_IDS(info)	 \
 	INTEL_SKL_GT1_IDS(info), \