[RFC,3/4] drm/etnaviv: Change order of enabling clocks to fix boot on i.MX8MM
diff mbox series

Message ID 20200430124602.14463-4-frieder.schrempf@kontron.de
State New
Headers show
Series
  • Add support for i.MX8MM GPUs through Etnaviv
Related show

Commit Message

Frieder Schrempf April 30, 2020, 12:46 p.m. UTC
From: Frieder Schrempf <frieder.schrempf@kontron.de>

On some i.MX8MM devices the boot hangs when enabling the GPU clocks.
Changing the order of clock initalization to

core -> shader -> bus -> reg

fixes the issue. This is the same order used in the imx platform code
of the downstream GPU driver in the NXP kernel [1]. For the sake of
consistency we also adjust the order of disabling the clocks to the
reverse.

[1] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/mxc/gpu-viv/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx.c?h=imx_5.4.3_2.0.0#n1538

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
---
 drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 42 +++++++++++++--------------
 1 file changed, 21 insertions(+), 21 deletions(-)

Comments

Lucas Stach April 30, 2020, 2:35 p.m. UTC | #1
Am Donnerstag, den 30.04.2020, 12:46 +0000 schrieb Schrempf Frieder:
> From: Frieder Schrempf <frieder.schrempf@kontron.de>
> 
> On some i.MX8MM devices the boot hangs when enabling the GPU clocks.
> Changing the order of clock initalization to
> 
> core -> shader -> bus -> reg
> 
> fixes the issue. This is the same order used in the imx platform code
> of the downstream GPU driver in the NXP kernel [1]. For the sake of
> consistency we also adjust the order of disabling the clocks to the
> reverse.
> 
> [1] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/mxc/gpu-viv/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx.c?h=imx_5.4.3_2.0.0#n1538

I don't see why the order of the clocks is important. Is this really a
GPU issue? As in: does a GPU access hang when enabling the clocks in
the wrong order? Or is this a clock driver issue with a clock access
hanging due to an upstream clock still being disabled?

Regards,
Lucas

> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
> ---
>  drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 42 +++++++++++++--------------
>  1 file changed, 21 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> index 7b138d4dd068..424b2e5951f0 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> @@ -1487,55 +1487,55 @@ static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
>  {
>  	int ret;
>  
> -	if (gpu->clk_reg) {
> -		ret = clk_prepare_enable(gpu->clk_reg);
> +	if (gpu->clk_core) {
> +		ret = clk_prepare_enable(gpu->clk_core);
>  		if (ret)
>  			return ret;
>  	}
>  
> -	if (gpu->clk_bus) {
> -		ret = clk_prepare_enable(gpu->clk_bus);
> +	if (gpu->clk_shader) {
> +		ret = clk_prepare_enable(gpu->clk_shader);
>  		if (ret)
> -			goto disable_clk_reg;
> +			goto disable_clk_core;
>  	}
>  
> -	if (gpu->clk_core) {
> -		ret = clk_prepare_enable(gpu->clk_core);
> +	if (gpu->clk_bus) {
> +		ret = clk_prepare_enable(gpu->clk_bus);
>  		if (ret)
> -			goto disable_clk_bus;
> +			goto disable_clk_shader;
>  	}
>  
> -	if (gpu->clk_shader) {
> -		ret = clk_prepare_enable(gpu->clk_shader);
> +	if (gpu->clk_reg) {
> +		ret = clk_prepare_enable(gpu->clk_reg);
>  		if (ret)
> -			goto disable_clk_core;
> +			goto disable_clk_bus;
>  	}
>  
>  	return 0;
>  
> -disable_clk_core:
> -	if (gpu->clk_core)
> -		clk_disable_unprepare(gpu->clk_core);
>  disable_clk_bus:
>  	if (gpu->clk_bus)
>  		clk_disable_unprepare(gpu->clk_bus);
> -disable_clk_reg:
> -	if (gpu->clk_reg)
> -		clk_disable_unprepare(gpu->clk_reg);
> +disable_clk_shader:
> +	if (gpu->clk_shader)
> +		clk_disable_unprepare(gpu->clk_shader);
> +disable_clk_core:
> +	if (gpu->clk_core)
> +		clk_disable_unprepare(gpu->clk_core);
>  
>  	return ret;
>  }
>  
>  static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
>  {
> +	if (gpu->clk_reg)
> +		clk_disable_unprepare(gpu->clk_reg);
> +	if (gpu->clk_bus)
> +		clk_disable_unprepare(gpu->clk_bus);
>  	if (gpu->clk_shader)
>  		clk_disable_unprepare(gpu->clk_shader);
>  	if (gpu->clk_core)
>  		clk_disable_unprepare(gpu->clk_core);
> -	if (gpu->clk_bus)
> -		clk_disable_unprepare(gpu->clk_bus);
> -	if (gpu->clk_reg)
> -		clk_disable_unprepare(gpu->clk_reg);
>  
>  	return 0;
>  }
Frieder Schrempf April 30, 2020, 3:35 p.m. UTC | #2
On 30.04.20 16:35, Lucas Stach wrote:
> Am Donnerstag, den 30.04.2020, 12:46 +0000 schrieb Schrempf Frieder:
>> From: Frieder Schrempf <frieder.schrempf@kontron.de>
>>
>> On some i.MX8MM devices the boot hangs when enabling the GPU clocks.
>> Changing the order of clock initalization to
>>
>> core -> shader -> bus -> reg
>>
>> fixes the issue. This is the same order used in the imx platform code
>> of the downstream GPU driver in the NXP kernel [1]. For the sake of
>> consistency we also adjust the order of disabling the clocks to the
>> reverse.
>>
>> [1] https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fsource.codeaurora.org%2Fexternal%2Fimx%2Flinux-imx%2Ftree%2Fdrivers%2Fmxc%2Fgpu-viv%2Fhal%2Fos%2Flinux%2Fkernel%2Fplatform%2Ffreescale%2Fgc_hal_kernel_platform_imx.c%3Fh%3Dimx_5.4.3_2.0.0%23n1538&amp;data=02%7C01%7Cfrieder.schrempf%40kontron.de%7Cdae15f14ed4a4999065508d7ed13ae87%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637238541095594019&amp;sdata=%2BImteXNH%2FqJDionnJVHtjVnXJk%2BG%2BVlgvBdRGfnlQro%3D&amp;reserved=0
> 
> I don't see why the order of the clocks is important. Is this really a
> GPU issue? As in: does a GPU access hang when enabling the clocks in
> the wrong order? Or is this a clock driver issue with a clock access
> hanging due to an upstream clock still being disabled?

Actually you might be right with this being a clock driver issue. The 
hanging happens while enabling the clocks (unrelated to any GPU register 
access). The strange thing is that most of the devices we have don't 
care and work as is and some devices reliably fail each time when 
enabling the clocks in the "wrong" order.

So I guess this could indeed be some clock being enabled with an 
upstream PLL not having locked yet or something.

> 
> Regards,
> Lucas
> 
>> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
>> ---
>>   drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 42 +++++++++++++--------------
>>   1 file changed, 21 insertions(+), 21 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
>> index 7b138d4dd068..424b2e5951f0 100644
>> --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
>> +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
>> @@ -1487,55 +1487,55 @@ static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
>>   {
>>   	int ret;
>>   
>> -	if (gpu->clk_reg) {
>> -		ret = clk_prepare_enable(gpu->clk_reg);
>> +	if (gpu->clk_core) {
>> +		ret = clk_prepare_enable(gpu->clk_core);
>>   		if (ret)
>>   			return ret;
>>   	}
>>   
>> -	if (gpu->clk_bus) {
>> -		ret = clk_prepare_enable(gpu->clk_bus);
>> +	if (gpu->clk_shader) {
>> +		ret = clk_prepare_enable(gpu->clk_shader);
>>   		if (ret)
>> -			goto disable_clk_reg;
>> +			goto disable_clk_core;
>>   	}
>>   
>> -	if (gpu->clk_core) {
>> -		ret = clk_prepare_enable(gpu->clk_core);
>> +	if (gpu->clk_bus) {
>> +		ret = clk_prepare_enable(gpu->clk_bus);
>>   		if (ret)
>> -			goto disable_clk_bus;
>> +			goto disable_clk_shader;
>>   	}
>>   
>> -	if (gpu->clk_shader) {
>> -		ret = clk_prepare_enable(gpu->clk_shader);
>> +	if (gpu->clk_reg) {
>> +		ret = clk_prepare_enable(gpu->clk_reg);
>>   		if (ret)
>> -			goto disable_clk_core;
>> +			goto disable_clk_bus;
>>   	}
>>   
>>   	return 0;
>>   
>> -disable_clk_core:
>> -	if (gpu->clk_core)
>> -		clk_disable_unprepare(gpu->clk_core);
>>   disable_clk_bus:
>>   	if (gpu->clk_bus)
>>   		clk_disable_unprepare(gpu->clk_bus);
>> -disable_clk_reg:
>> -	if (gpu->clk_reg)
>> -		clk_disable_unprepare(gpu->clk_reg);
>> +disable_clk_shader:
>> +	if (gpu->clk_shader)
>> +		clk_disable_unprepare(gpu->clk_shader);
>> +disable_clk_core:
>> +	if (gpu->clk_core)
>> +		clk_disable_unprepare(gpu->clk_core);
>>   
>>   	return ret;
>>   }
>>   
>>   static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
>>   {
>> +	if (gpu->clk_reg)
>> +		clk_disable_unprepare(gpu->clk_reg);
>> +	if (gpu->clk_bus)
>> +		clk_disable_unprepare(gpu->clk_bus);
>>   	if (gpu->clk_shader)
>>   		clk_disable_unprepare(gpu->clk_shader);
>>   	if (gpu->clk_core)
>>   		clk_disable_unprepare(gpu->clk_core);
>> -	if (gpu->clk_bus)
>> -		clk_disable_unprepare(gpu->clk_bus);
>> -	if (gpu->clk_reg)
>> -		clk_disable_unprepare(gpu->clk_reg);
>>   
>>   	return 0;
>>   }
>
Peng Fan May 1, 2020, 12:36 p.m. UTC | #3
> Subject: Re: [RFC PATCH 3/4] drm/etnaviv: Change order of enabling clocks to
> fix boot on i.MX8MM
> 
> On 30.04.20 16:35, Lucas Stach wrote:
> > Am Donnerstag, den 30.04.2020, 12:46 +0000 schrieb Schrempf Frieder:
> >> From: Frieder Schrempf <frieder.schrempf@kontron.de>
> >>
> >> On some i.MX8MM devices the boot hangs when enabling the GPU clocks.
> >> Changing the order of clock initalization to
> >>
> >> core -> shader -> bus -> reg
> >>
> >> fixes the issue. This is the same order used in the imx platform code
> >> of the downstream GPU driver in the NXP kernel [1]. For the sake of
> >> consistency we also adjust the order of disabling the clocks to the
> >> reverse.
> >>
> >> [1]
> >> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fsou
> >>
> rce.codeaurora.org%2Fexternal%2Fimx%2Flinux-imx%2Ftree%2Fdrivers%2F
> mx
> >>
> c%2Fgpu-viv%2Fhal%2Fos%2Flinux%2Fkernel%2Fplatform%2Ffreescale%2Fgc
> _h
> >>
> al_kernel_platform_imx.c%3Fh%3Dimx_5.4.3_2.0.0%23n1538&amp;data=02
> %7C
> >>
> 01%7Cpeng.fan%40nxp.com%7Cdc7da53f665e4f567e3008d7ed1c27e0%7C6
> 86ea1d3
> >>
> bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637238577497969787&amp;sda
> ta=QRHzu
> >> C6gSKy%2F6y2FTRvlNF5t7DmJIvTgBESYKchI%2FDw%3D&amp;reserved=0
> >
> > I don't see why the order of the clocks is important. Is this really a
> > GPU issue? As in: does a GPU access hang when enabling the clocks in
> > the wrong order? Or is this a clock driver issue with a clock access
> > hanging due to an upstream clock still being disabled?
> 
> Actually you might be right with this being a clock driver issue. The hanging
> happens while enabling the clocks (unrelated to any GPU register access). The
> strange thing is that most of the devices we have don't care and work as is
> and some devices reliably fail each time when enabling the clocks in the
> "wrong" order.
> 
> So I guess this could indeed be some clock being enabled with an upstream
> PLL not having locked yet or something.

https://patchwork.kernel.org/cover/11433775/

Will this pachset help?

The i.MX8M CCM root mux code in Linux needs a fix.

Regards,
Peng.

> 
> >
> > Regards,
> > Lucas
> >
> >> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
> >> ---
> >>   drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 42
> +++++++++++++--------------
> >>   1 file changed, 21 insertions(+), 21 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> >> b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> >> index 7b138d4dd068..424b2e5951f0 100644
> >> --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> >> +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> >> @@ -1487,55 +1487,55 @@ static int etnaviv_gpu_clk_enable(struct
> etnaviv_gpu *gpu)
> >>   {
> >>   	int ret;
> >>
> >> -	if (gpu->clk_reg) {
> >> -		ret = clk_prepare_enable(gpu->clk_reg);
> >> +	if (gpu->clk_core) {
> >> +		ret = clk_prepare_enable(gpu->clk_core);
> >>   		if (ret)
> >>   			return ret;
> >>   	}
> >>
> >> -	if (gpu->clk_bus) {
> >> -		ret = clk_prepare_enable(gpu->clk_bus);
> >> +	if (gpu->clk_shader) {
> >> +		ret = clk_prepare_enable(gpu->clk_shader);
> >>   		if (ret)
> >> -			goto disable_clk_reg;
> >> +			goto disable_clk_core;
> >>   	}
> >>
> >> -	if (gpu->clk_core) {
> >> -		ret = clk_prepare_enable(gpu->clk_core);
> >> +	if (gpu->clk_bus) {
> >> +		ret = clk_prepare_enable(gpu->clk_bus);
> >>   		if (ret)
> >> -			goto disable_clk_bus;
> >> +			goto disable_clk_shader;
> >>   	}
> >>
> >> -	if (gpu->clk_shader) {
> >> -		ret = clk_prepare_enable(gpu->clk_shader);
> >> +	if (gpu->clk_reg) {
> >> +		ret = clk_prepare_enable(gpu->clk_reg);
> >>   		if (ret)
> >> -			goto disable_clk_core;
> >> +			goto disable_clk_bus;
> >>   	}
> >>
> >>   	return 0;
> >>
> >> -disable_clk_core:
> >> -	if (gpu->clk_core)
> >> -		clk_disable_unprepare(gpu->clk_core);
> >>   disable_clk_bus:
> >>   	if (gpu->clk_bus)
> >>   		clk_disable_unprepare(gpu->clk_bus);
> >> -disable_clk_reg:
> >> -	if (gpu->clk_reg)
> >> -		clk_disable_unprepare(gpu->clk_reg);
> >> +disable_clk_shader:
> >> +	if (gpu->clk_shader)
> >> +		clk_disable_unprepare(gpu->clk_shader);
> >> +disable_clk_core:
> >> +	if (gpu->clk_core)
> >> +		clk_disable_unprepare(gpu->clk_core);
> >>
> >>   	return ret;
> >>   }
> >>
> >>   static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
> >>   {
> >> +	if (gpu->clk_reg)
> >> +		clk_disable_unprepare(gpu->clk_reg);
> >> +	if (gpu->clk_bus)
> >> +		clk_disable_unprepare(gpu->clk_bus);
> >>   	if (gpu->clk_shader)
> >>   		clk_disable_unprepare(gpu->clk_shader);
> >>   	if (gpu->clk_core)
> >>   		clk_disable_unprepare(gpu->clk_core);
> >> -	if (gpu->clk_bus)
> >> -		clk_disable_unprepare(gpu->clk_bus);
> >> -	if (gpu->clk_reg)
> >> -		clk_disable_unprepare(gpu->clk_reg);
> >>
> >>   	return 0;
> >>   }
> >
Frieder Schrempf May 6, 2020, 11:27 a.m. UTC | #4
Hi Peng,

On 01.05.20 14:36, Peng Fan wrote:
>> Subject: Re: [RFC PATCH 3/4] drm/etnaviv: Change order of enabling clocks to
>> fix boot on i.MX8MM
>>
>> On 30.04.20 16:35, Lucas Stach wrote:
>>> Am Donnerstag, den 30.04.2020, 12:46 +0000 schrieb Schrempf Frieder:
>>>> From: Frieder Schrempf <frieder.schrempf@kontron.de>
>>>>
>>>> On some i.MX8MM devices the boot hangs when enabling the GPU clocks.
>>>> Changing the order of clock initalization to
>>>>
>>>> core -> shader -> bus -> reg
>>>>
>>>> fixes the issue. This is the same order used in the imx platform code
>>>> of the downstream GPU driver in the NXP kernel [1]. For the sake of
>>>> consistency we also adjust the order of disabling the clocks to the
>>>> reverse.
>>>>
>>>> [1]
>>>> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fsou
>>>>
>> rce.codeaurora.org%2Fexternal%2Fimx%2Flinux-imx%2Ftree%2Fdrivers%2F
>> mx
>>>>
>> c%2Fgpu-viv%2Fhal%2Fos%2Flinux%2Fkernel%2Fplatform%2Ffreescale%2Fgc
>> _h
>>>>
>> al_kernel_platform_imx.c%3Fh%3Dimx_5.4.3_2.0.0%23n1538&amp;data=02
>> %7C
>>>>
>> 01%7Cpeng.fan%40nxp.com%7Cdc7da53f665e4f567e3008d7ed1c27e0%7C6
>> 86ea1d3
>>>>
>> bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637238577497969787&amp;sda
>> ta=QRHzu
>>>> C6gSKy%2F6y2FTRvlNF5t7DmJIvTgBESYKchI%2FDw%3D&amp;reserved=0
>>>
>>> I don't see why the order of the clocks is important. Is this really a
>>> GPU issue? As in: does a GPU access hang when enabling the clocks in
>>> the wrong order? Or is this a clock driver issue with a clock access
>>> hanging due to an upstream clock still being disabled?
>>
>> Actually you might be right with this being a clock driver issue. The hanging
>> happens while enabling the clocks (unrelated to any GPU register access). The
>> strange thing is that most of the devices we have don't care and work as is
>> and some devices reliably fail each time when enabling the clocks in the
>> "wrong" order.
>>
>> So I guess this could indeed be some clock being enabled with an upstream
>> PLL not having locked yet or something.
> 
> https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.kernel.org%2Fcover%2F11433775%2F&amp;data=02%7C01%7Cfrieder.schrempf%40kontron.de%7C1014be5f9b8b4d0c6e8108d7edcc5bde%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637239334279684748&amp;sdata=UwVVzPEvNOP6I4g78uG5O9jVYmHwqyo6hj97wvtlzs0%3D&amp;reserved=0
> 
> Will this pachset help?

Thanks for the pointer. Unfortunately the clock patches don't help. I 
tried with 5.7-rc4 and your patches on top and the issue still persists.

Also I found out that changing the order of the clock initialization as 
proposed, does not fix the problem, either. On some boards it helps, 
others still hang when the clocks are initialized.

Thanks,
Frieder

> 
> The i.MX8M CCM root mux code in Linux needs a fix.
> 
> Regards,
> Peng.
> 
>>
>>>
>>> Regards,
>>> Lucas
>>>
>>>> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
>>>> ---
>>>>    drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 42
>> +++++++++++++--------------
>>>>    1 file changed, 21 insertions(+), 21 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
>>>> b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
>>>> index 7b138d4dd068..424b2e5951f0 100644
>>>> --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
>>>> +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
>>>> @@ -1487,55 +1487,55 @@ static int etnaviv_gpu_clk_enable(struct
>> etnaviv_gpu *gpu)
>>>>    {
>>>>    	int ret;
>>>>
>>>> -	if (gpu->clk_reg) {
>>>> -		ret = clk_prepare_enable(gpu->clk_reg);
>>>> +	if (gpu->clk_core) {
>>>> +		ret = clk_prepare_enable(gpu->clk_core);
>>>>    		if (ret)
>>>>    			return ret;
>>>>    	}
>>>>
>>>> -	if (gpu->clk_bus) {
>>>> -		ret = clk_prepare_enable(gpu->clk_bus);
>>>> +	if (gpu->clk_shader) {
>>>> +		ret = clk_prepare_enable(gpu->clk_shader);
>>>>    		if (ret)
>>>> -			goto disable_clk_reg;
>>>> +			goto disable_clk_core;
>>>>    	}
>>>>
>>>> -	if (gpu->clk_core) {
>>>> -		ret = clk_prepare_enable(gpu->clk_core);
>>>> +	if (gpu->clk_bus) {
>>>> +		ret = clk_prepare_enable(gpu->clk_bus);
>>>>    		if (ret)
>>>> -			goto disable_clk_bus;
>>>> +			goto disable_clk_shader;
>>>>    	}
>>>>
>>>> -	if (gpu->clk_shader) {
>>>> -		ret = clk_prepare_enable(gpu->clk_shader);
>>>> +	if (gpu->clk_reg) {
>>>> +		ret = clk_prepare_enable(gpu->clk_reg);
>>>>    		if (ret)
>>>> -			goto disable_clk_core;
>>>> +			goto disable_clk_bus;
>>>>    	}
>>>>
>>>>    	return 0;
>>>>
>>>> -disable_clk_core:
>>>> -	if (gpu->clk_core)
>>>> -		clk_disable_unprepare(gpu->clk_core);
>>>>    disable_clk_bus:
>>>>    	if (gpu->clk_bus)
>>>>    		clk_disable_unprepare(gpu->clk_bus);
>>>> -disable_clk_reg:
>>>> -	if (gpu->clk_reg)
>>>> -		clk_disable_unprepare(gpu->clk_reg);
>>>> +disable_clk_shader:
>>>> +	if (gpu->clk_shader)
>>>> +		clk_disable_unprepare(gpu->clk_shader);
>>>> +disable_clk_core:
>>>> +	if (gpu->clk_core)
>>>> +		clk_disable_unprepare(gpu->clk_core);
>>>>
>>>>    	return ret;
>>>>    }
>>>>
>>>>    static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
>>>>    {
>>>> +	if (gpu->clk_reg)
>>>> +		clk_disable_unprepare(gpu->clk_reg);
>>>> +	if (gpu->clk_bus)
>>>> +		clk_disable_unprepare(gpu->clk_bus);
>>>>    	if (gpu->clk_shader)
>>>>    		clk_disable_unprepare(gpu->clk_shader);
>>>>    	if (gpu->clk_core)
>>>>    		clk_disable_unprepare(gpu->clk_core);
>>>> -	if (gpu->clk_bus)
>>>> -		clk_disable_unprepare(gpu->clk_bus);
>>>> -	if (gpu->clk_reg)
>>>> -		clk_disable_unprepare(gpu->clk_reg);
>>>>
>>>>    	return 0;
>>>>    }
>>>
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Patch
diff mbox series

diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index 7b138d4dd068..424b2e5951f0 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -1487,55 +1487,55 @@  static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
 {
 	int ret;
 
-	if (gpu->clk_reg) {
-		ret = clk_prepare_enable(gpu->clk_reg);
+	if (gpu->clk_core) {
+		ret = clk_prepare_enable(gpu->clk_core);
 		if (ret)
 			return ret;
 	}
 
-	if (gpu->clk_bus) {
-		ret = clk_prepare_enable(gpu->clk_bus);
+	if (gpu->clk_shader) {
+		ret = clk_prepare_enable(gpu->clk_shader);
 		if (ret)
-			goto disable_clk_reg;
+			goto disable_clk_core;
 	}
 
-	if (gpu->clk_core) {
-		ret = clk_prepare_enable(gpu->clk_core);
+	if (gpu->clk_bus) {
+		ret = clk_prepare_enable(gpu->clk_bus);
 		if (ret)
-			goto disable_clk_bus;
+			goto disable_clk_shader;
 	}
 
-	if (gpu->clk_shader) {
-		ret = clk_prepare_enable(gpu->clk_shader);
+	if (gpu->clk_reg) {
+		ret = clk_prepare_enable(gpu->clk_reg);
 		if (ret)
-			goto disable_clk_core;
+			goto disable_clk_bus;
 	}
 
 	return 0;
 
-disable_clk_core:
-	if (gpu->clk_core)
-		clk_disable_unprepare(gpu->clk_core);
 disable_clk_bus:
 	if (gpu->clk_bus)
 		clk_disable_unprepare(gpu->clk_bus);
-disable_clk_reg:
-	if (gpu->clk_reg)
-		clk_disable_unprepare(gpu->clk_reg);
+disable_clk_shader:
+	if (gpu->clk_shader)
+		clk_disable_unprepare(gpu->clk_shader);
+disable_clk_core:
+	if (gpu->clk_core)
+		clk_disable_unprepare(gpu->clk_core);
 
 	return ret;
 }
 
 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
 {
+	if (gpu->clk_reg)
+		clk_disable_unprepare(gpu->clk_reg);
+	if (gpu->clk_bus)
+		clk_disable_unprepare(gpu->clk_bus);
 	if (gpu->clk_shader)
 		clk_disable_unprepare(gpu->clk_shader);
 	if (gpu->clk_core)
 		clk_disable_unprepare(gpu->clk_core);
-	if (gpu->clk_bus)
-		clk_disable_unprepare(gpu->clk_bus);
-	if (gpu->clk_reg)
-		clk_disable_unprepare(gpu->clk_reg);
 
 	return 0;
 }