| Message ID | 1588426445-24344-5-git-send-email-anshuman.khandual@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes | expand |
On Sat, May 02, 2020 at 07:03:53PM +0530, Anshuman Khandual wrote: > This adds basic building blocks required for ID_PFR2 CPU register which > provides information about the AArch32 programmers model which must be > interpreted along with ID_PFR0 and ID_PFR1 CPU registers. This is added > per ARM DDI 0487F.a specification. > > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Marc Zyngier <maz@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: James Morse <james.morse@arm.com> > Cc: Suzuki K Poulose <suzuki.poulose@arm.com> > Cc: kvmarm@lists.cs.columbia.edu > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > > Suggested-by: Mark Rutland <mark.rutland@arm.com> > Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> > --- > arch/arm64/include/asm/cpu.h | 1 + > arch/arm64/include/asm/sysreg.h | 4 ++++ > arch/arm64/kernel/cpufeature.c | 11 +++++++++++ > arch/arm64/kernel/cpuinfo.c | 1 + > arch/arm64/kvm/sys_regs.c | 2 +- > 5 files changed, 18 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h > index b4a40535a3d8..464e828a994d 100644 > --- a/arch/arm64/include/asm/cpu.h > +++ b/arch/arm64/include/asm/cpu.h > @@ -46,6 +46,7 @@ struct cpuinfo_arm64 { > u32 reg_id_mmfr3; > u32 reg_id_pfr0; > u32 reg_id_pfr1; > + u32 reg_id_pfr2; > > u32 reg_mvfr0; > u32 reg_mvfr1; > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index e5317a6367b6..c977449e02db 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -153,6 +153,7 @@ > #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) > #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) > #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) > +#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) nit: but please group these defines by name rather than encoding. Will
On Tue, May 05, 2020 at 12:12:41PM +0100, Will Deacon wrote: > On Sat, May 02, 2020 at 07:03:53PM +0530, Anshuman Khandual wrote: > > This adds basic building blocks required for ID_PFR2 CPU register which > > provides information about the AArch32 programmers model which must be > > interpreted along with ID_PFR0 and ID_PFR1 CPU registers. This is added > > per ARM DDI 0487F.a specification. > > > > Cc: Catalin Marinas <catalin.marinas@arm.com> > > Cc: Will Deacon <will@kernel.org> > > Cc: Marc Zyngier <maz@kernel.org> > > Cc: Mark Rutland <mark.rutland@arm.com> > > Cc: James Morse <james.morse@arm.com> > > Cc: Suzuki K Poulose <suzuki.poulose@arm.com> > > Cc: kvmarm@lists.cs.columbia.edu > > Cc: linux-arm-kernel@lists.infradead.org > > Cc: linux-kernel@vger.kernel.org > > > > Suggested-by: Mark Rutland <mark.rutland@arm.com> > > Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> > > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> > > --- > > arch/arm64/include/asm/cpu.h | 1 + > > arch/arm64/include/asm/sysreg.h | 4 ++++ > > arch/arm64/kernel/cpufeature.c | 11 +++++++++++ > > arch/arm64/kernel/cpuinfo.c | 1 + > > arch/arm64/kvm/sys_regs.c | 2 +- > > 5 files changed, 18 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h > > index b4a40535a3d8..464e828a994d 100644 > > --- a/arch/arm64/include/asm/cpu.h > > +++ b/arch/arm64/include/asm/cpu.h > > @@ -46,6 +46,7 @@ struct cpuinfo_arm64 { > > u32 reg_id_mmfr3; > > u32 reg_id_pfr0; > > u32 reg_id_pfr1; > > + u32 reg_id_pfr2; > > > > u32 reg_mvfr0; > > u32 reg_mvfr1; > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > > index e5317a6367b6..c977449e02db 100644 > > --- a/arch/arm64/include/asm/sysreg.h > > +++ b/arch/arm64/include/asm/sysreg.h > > @@ -153,6 +153,7 @@ > > #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) > > #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) > > #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) > > +#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) > > nit: but please group these defines by name rather than encoding. So far we've *always* grouped these by encoding in this file, so can we keep things that way for now? Otherwise we're inconsistent with both schemes. Mark.
On Tue, May 05, 2020 at 12:16:07PM +0100, Mark Rutland wrote: > On Tue, May 05, 2020 at 12:12:41PM +0100, Will Deacon wrote: > > On Sat, May 02, 2020 at 07:03:53PM +0530, Anshuman Khandual wrote: > > > This adds basic building blocks required for ID_PFR2 CPU register which > > > provides information about the AArch32 programmers model which must be > > > interpreted along with ID_PFR0 and ID_PFR1 CPU registers. This is added > > > per ARM DDI 0487F.a specification. > > > > > > Cc: Catalin Marinas <catalin.marinas@arm.com> > > > Cc: Will Deacon <will@kernel.org> > > > Cc: Marc Zyngier <maz@kernel.org> > > > Cc: Mark Rutland <mark.rutland@arm.com> > > > Cc: James Morse <james.morse@arm.com> > > > Cc: Suzuki K Poulose <suzuki.poulose@arm.com> > > > Cc: kvmarm@lists.cs.columbia.edu > > > Cc: linux-arm-kernel@lists.infradead.org > > > Cc: linux-kernel@vger.kernel.org > > > > > > Suggested-by: Mark Rutland <mark.rutland@arm.com> > > > Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> > > > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> > > > --- > > > arch/arm64/include/asm/cpu.h | 1 + > > > arch/arm64/include/asm/sysreg.h | 4 ++++ > > > arch/arm64/kernel/cpufeature.c | 11 +++++++++++ > > > arch/arm64/kernel/cpuinfo.c | 1 + > > > arch/arm64/kvm/sys_regs.c | 2 +- > > > 5 files changed, 18 insertions(+), 1 deletion(-) > > > > > > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h > > > index b4a40535a3d8..464e828a994d 100644 > > > --- a/arch/arm64/include/asm/cpu.h > > > +++ b/arch/arm64/include/asm/cpu.h > > > @@ -46,6 +46,7 @@ struct cpuinfo_arm64 { > > > u32 reg_id_mmfr3; > > > u32 reg_id_pfr0; > > > u32 reg_id_pfr1; > > > + u32 reg_id_pfr2; > > > > > > u32 reg_mvfr0; > > > u32 reg_mvfr1; > > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > > > index e5317a6367b6..c977449e02db 100644 > > > --- a/arch/arm64/include/asm/sysreg.h > > > +++ b/arch/arm64/include/asm/sysreg.h > > > @@ -153,6 +153,7 @@ > > > #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) > > > #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) > > > #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) > > > +#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) > > > > nit: but please group these defines by name rather than encoding. > > So far we've *always* grouped these by encoding in this file, so can we > keep things that way for now? Otherwise we're inconsistent with both > schemes. Unless you just meant "please put a newline before this" to avoid grouping without affecting ordering, in which case agreed! Mark.
On Tue, May 05, 2020 at 12:16:07PM +0100, Mark Rutland wrote: > On Tue, May 05, 2020 at 12:12:41PM +0100, Will Deacon wrote: > > On Sat, May 02, 2020 at 07:03:53PM +0530, Anshuman Khandual wrote: > > > This adds basic building blocks required for ID_PFR2 CPU register which > > > provides information about the AArch32 programmers model which must be > > > interpreted along with ID_PFR0 and ID_PFR1 CPU registers. This is added > > > per ARM DDI 0487F.a specification. > > > > > > Cc: Catalin Marinas <catalin.marinas@arm.com> > > > Cc: Will Deacon <will@kernel.org> > > > Cc: Marc Zyngier <maz@kernel.org> > > > Cc: Mark Rutland <mark.rutland@arm.com> > > > Cc: James Morse <james.morse@arm.com> > > > Cc: Suzuki K Poulose <suzuki.poulose@arm.com> > > > Cc: kvmarm@lists.cs.columbia.edu > > > Cc: linux-arm-kernel@lists.infradead.org > > > Cc: linux-kernel@vger.kernel.org > > > > > > Suggested-by: Mark Rutland <mark.rutland@arm.com> > > > Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> > > > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> > > > --- > > > arch/arm64/include/asm/cpu.h | 1 + > > > arch/arm64/include/asm/sysreg.h | 4 ++++ > > > arch/arm64/kernel/cpufeature.c | 11 +++++++++++ > > > arch/arm64/kernel/cpuinfo.c | 1 + > > > arch/arm64/kvm/sys_regs.c | 2 +- > > > 5 files changed, 18 insertions(+), 1 deletion(-) > > > > > > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h > > > index b4a40535a3d8..464e828a994d 100644 > > > --- a/arch/arm64/include/asm/cpu.h > > > +++ b/arch/arm64/include/asm/cpu.h > > > @@ -46,6 +46,7 @@ struct cpuinfo_arm64 { > > > u32 reg_id_mmfr3; > > > u32 reg_id_pfr0; > > > u32 reg_id_pfr1; > > > + u32 reg_id_pfr2; > > > > > > u32 reg_mvfr0; > > > u32 reg_mvfr1; > > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > > > index e5317a6367b6..c977449e02db 100644 > > > --- a/arch/arm64/include/asm/sysreg.h > > > +++ b/arch/arm64/include/asm/sysreg.h > > > @@ -153,6 +153,7 @@ > > > #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) > > > #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) > > > #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) > > > +#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) > > > > nit: but please group these defines by name rather than encoding. > > So far we've *always* grouped these by encoding in this file, so can we > keep things that way for now? Otherwise we're inconsistent with both > schemes. Hmm, but it's really hard to read sorted that way and we'll end up with duplicate definitions like we had for some of the field offsets already. The only ID register that seems to be out of place atm is MMFR4, which I can move (see below) Will --->8 diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 2dd3f4ca9780..137201ea383b 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -140,6 +140,7 @@ #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) +#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) @@ -147,7 +148,6 @@ #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) -#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) #define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7) #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
On Tue, May 05, 2020 at 12:27:19PM +0100, Will Deacon wrote: > On Tue, May 05, 2020 at 12:16:07PM +0100, Mark Rutland wrote: > > On Tue, May 05, 2020 at 12:12:41PM +0100, Will Deacon wrote: > > > On Sat, May 02, 2020 at 07:03:53PM +0530, Anshuman Khandual wrote: > > > > This adds basic building blocks required for ID_PFR2 CPU register which > > > > provides information about the AArch32 programmers model which must be > > > > interpreted along with ID_PFR0 and ID_PFR1 CPU registers. This is added > > > > per ARM DDI 0487F.a specification. > > > > > > > > Cc: Catalin Marinas <catalin.marinas@arm.com> > > > > Cc: Will Deacon <will@kernel.org> > > > > Cc: Marc Zyngier <maz@kernel.org> > > > > Cc: Mark Rutland <mark.rutland@arm.com> > > > > Cc: James Morse <james.morse@arm.com> > > > > Cc: Suzuki K Poulose <suzuki.poulose@arm.com> > > > > Cc: kvmarm@lists.cs.columbia.edu > > > > Cc: linux-arm-kernel@lists.infradead.org > > > > Cc: linux-kernel@vger.kernel.org > > > > > > > > Suggested-by: Mark Rutland <mark.rutland@arm.com> > > > > Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> > > > > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> > > > > --- > > > > arch/arm64/include/asm/cpu.h | 1 + > > > > arch/arm64/include/asm/sysreg.h | 4 ++++ > > > > arch/arm64/kernel/cpufeature.c | 11 +++++++++++ > > > > arch/arm64/kernel/cpuinfo.c | 1 + > > > > arch/arm64/kvm/sys_regs.c | 2 +- > > > > 5 files changed, 18 insertions(+), 1 deletion(-) > > > > > > > > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h > > > > index b4a40535a3d8..464e828a994d 100644 > > > > --- a/arch/arm64/include/asm/cpu.h > > > > +++ b/arch/arm64/include/asm/cpu.h > > > > @@ -46,6 +46,7 @@ struct cpuinfo_arm64 { > > > > u32 reg_id_mmfr3; > > > > u32 reg_id_pfr0; > > > > u32 reg_id_pfr1; > > > > + u32 reg_id_pfr2; > > > > > > > > u32 reg_mvfr0; > > > > u32 reg_mvfr1; > > > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > > > > index e5317a6367b6..c977449e02db 100644 > > > > --- a/arch/arm64/include/asm/sysreg.h > > > > +++ b/arch/arm64/include/asm/sysreg.h > > > > @@ -153,6 +153,7 @@ > > > > #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) > > > > #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) > > > > #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) > > > > +#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) > > > > > > nit: but please group these defines by name rather than encoding. > > > > So far we've *always* grouped these by encoding in this file, so can we > > keep things that way for now? Otherwise we're inconsistent with both > > schemes. > > Hmm, but it's really hard to read sorted that way and we'll end up with > duplicate definitions like we had for some of the field offsets already. I appreciate that, and don't disagree that the current scheme is not obvious. I just want to ensure that we don't make things less consistent, and if we're going to change the scheme in order to make that easier, it should be a separate patch. There'll be other changes like MMFR4_EL1, and we should probably add a comment as to what the policy is either way (e.g. if we're just grouping at the top level, or if that should be sorted too). Thanks, Mark. > The only ID register that seems to be out of place atm is MMFR4, which I > can move (see below) > > Will > > --->8 > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 2dd3f4ca9780..137201ea383b 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -140,6 +140,7 @@ > #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) > #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) > #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) > +#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) > > #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) > #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) > @@ -147,7 +148,6 @@ > #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) > #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) > #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) > -#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) > #define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7) > > #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
On Tue, May 05, 2020 at 12:50:54PM +0100, Mark Rutland wrote: > On Tue, May 05, 2020 at 12:27:19PM +0100, Will Deacon wrote: > > On Tue, May 05, 2020 at 12:16:07PM +0100, Mark Rutland wrote: > > > On Tue, May 05, 2020 at 12:12:41PM +0100, Will Deacon wrote: > > > > On Sat, May 02, 2020 at 07:03:53PM +0530, Anshuman Khandual wrote: > > > > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > > > > > index e5317a6367b6..c977449e02db 100644 > > > > > --- a/arch/arm64/include/asm/sysreg.h > > > > > +++ b/arch/arm64/include/asm/sysreg.h > > > > > @@ -153,6 +153,7 @@ > > > > > #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) > > > > > #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) > > > > > #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) > > > > > +#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) > > > > > > > > nit: but please group these defines by name rather than encoding. > > > > > > So far we've *always* grouped these by encoding in this file, so can we > > > keep things that way for now? Otherwise we're inconsistent with both > > > schemes. > > > > Hmm, but it's really hard to read sorted that way and we'll end up with > > duplicate definitions like we had for some of the field offsets already. > > I appreciate that, and don't disagree that the current scheme is not > obvious. > > I just want to ensure that we don't make things less consistent, and if > we're going to change the scheme in order to make that easier, it should > be a separate patch. There'll be other changes like MMFR4_EL1, and we > should probably add a comment as to what the policy is either way (e.g. > if we're just grouping at the top level, or if that should be sorted > too). Ok, I added a comment below. Will --->8 commit be7ab6a6cdb0a6d7b10883094c2adf96f5d4e1e8 Author: Will Deacon <will@kernel.org> Date: Tue May 5 13:08:02 2020 +0100 arm64: cpufeature: Group indexed system register definitions by name Some system registers contain an index in the name (e.g. ID_MMFR<n>_EL1) and, while this index often follows the register encoding, newer additions to the architecture are necessarily tacked on the end. Sorting these registers by encoding therefore becomes a bit of a mess. Group the indexed system register definitions by name so that it's easier to read and will hopefully reduce the chance of us accidentally introducing duplicate definitions in the future. Signed-off-by: Will Deacon <will@kernel.org> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 2dd3f4ca9780..194684301df0 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -105,6 +105,10 @@ #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) +/* + * System registers, organised loosely by encoding but grouped together + * where the architected name contains an index. e.g. ID_MMFR<n>_EL1. + */ #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0) #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2) @@ -140,6 +144,7 @@ #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) +#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) @@ -147,7 +152,6 @@ #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) -#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) #define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7) #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
On Tue, May 05, 2020 at 01:12:39PM +0100, Will Deacon wrote: > On Tue, May 05, 2020 at 12:50:54PM +0100, Mark Rutland wrote: > > On Tue, May 05, 2020 at 12:27:19PM +0100, Will Deacon wrote: > > > On Tue, May 05, 2020 at 12:16:07PM +0100, Mark Rutland wrote: > > > > On Tue, May 05, 2020 at 12:12:41PM +0100, Will Deacon wrote: > > > > > On Sat, May 02, 2020 at 07:03:53PM +0530, Anshuman Khandual wrote: > > > > > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > > > > > > index e5317a6367b6..c977449e02db 100644 > > > > > > --- a/arch/arm64/include/asm/sysreg.h > > > > > > +++ b/arch/arm64/include/asm/sysreg.h > > > > > > @@ -153,6 +153,7 @@ > > > > > > #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) > > > > > > #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) > > > > > > #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) > > > > > > +#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) > > > > > > > > > > nit: but please group these defines by name rather than encoding. > > > > > > > > So far we've *always* grouped these by encoding in this file, so can we > > > > keep things that way for now? Otherwise we're inconsistent with both > > > > schemes. > > > > > > Hmm, but it's really hard to read sorted that way and we'll end up with > > > duplicate definitions like we had for some of the field offsets already. > > > > I appreciate that, and don't disagree that the current scheme is not > > obvious. > > > > I just want to ensure that we don't make things less consistent, and if > > we're going to change the scheme in order to make that easier, it should > > be a separate patch. There'll be other changes like MMFR4_EL1, and we > > should probably add a comment as to what the policy is either way (e.g. > > if we're just grouping at the top level, or if that should be sorted > > too). > > Ok, I added a comment below. Thanks! Acked-by: Mark Rutland <mark.rutland@arm.com> Mark. > > Will > > --->8 > > commit be7ab6a6cdb0a6d7b10883094c2adf96f5d4e1e8 > Author: Will Deacon <will@kernel.org> > Date: Tue May 5 13:08:02 2020 +0100 > > arm64: cpufeature: Group indexed system register definitions by name > > Some system registers contain an index in the name (e.g. ID_MMFR<n>_EL1) > and, while this index often follows the register encoding, newer additions > to the architecture are necessarily tacked on the end. Sorting these > registers by encoding therefore becomes a bit of a mess. > > Group the indexed system register definitions by name so that it's easier to > read and will hopefully reduce the chance of us accidentally introducing > duplicate definitions in the future. > > Signed-off-by: Will Deacon <will@kernel.org> > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 2dd3f4ca9780..194684301df0 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -105,6 +105,10 @@ > #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) > #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) > > +/* > + * System registers, organised loosely by encoding but grouped together > + * where the architected name contains an index. e.g. ID_MMFR<n>_EL1. > + */ > #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) > #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0) > #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2) > @@ -140,6 +144,7 @@ > #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) > #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) > #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) > +#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) > > #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) > #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) > @@ -147,7 +152,6 @@ > #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) > #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) > #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) > -#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) > #define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7) > > #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) >
On 05/05/2020 04:42 PM, Will Deacon wrote: > On Sat, May 02, 2020 at 07:03:53PM +0530, Anshuman Khandual wrote: >> This adds basic building blocks required for ID_PFR2 CPU register which >> provides information about the AArch32 programmers model which must be >> interpreted along with ID_PFR0 and ID_PFR1 CPU registers. This is added >> per ARM DDI 0487F.a specification. >> >> Cc: Catalin Marinas <catalin.marinas@arm.com> >> Cc: Will Deacon <will@kernel.org> >> Cc: Marc Zyngier <maz@kernel.org> >> Cc: Mark Rutland <mark.rutland@arm.com> >> Cc: James Morse <james.morse@arm.com> >> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> >> Cc: kvmarm@lists.cs.columbia.edu >> Cc: linux-arm-kernel@lists.infradead.org >> Cc: linux-kernel@vger.kernel.org >> >> Suggested-by: Mark Rutland <mark.rutland@arm.com> >> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> >> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> >> --- >> arch/arm64/include/asm/cpu.h | 1 + >> arch/arm64/include/asm/sysreg.h | 4 ++++ >> arch/arm64/kernel/cpufeature.c | 11 +++++++++++ >> arch/arm64/kernel/cpuinfo.c | 1 + >> arch/arm64/kvm/sys_regs.c | 2 +- >> 5 files changed, 18 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h >> index b4a40535a3d8..464e828a994d 100644 >> --- a/arch/arm64/include/asm/cpu.h >> +++ b/arch/arm64/include/asm/cpu.h >> @@ -46,6 +46,7 @@ struct cpuinfo_arm64 { >> u32 reg_id_mmfr3; >> u32 reg_id_pfr0; >> u32 reg_id_pfr1; >> + u32 reg_id_pfr2; >> >> u32 reg_mvfr0; >> u32 reg_mvfr1; >> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h >> index e5317a6367b6..c977449e02db 100644 >> --- a/arch/arm64/include/asm/sysreg.h >> +++ b/arch/arm64/include/asm/sysreg.h >> @@ -153,6 +153,7 @@ >> #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) >> #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) >> #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) >> +#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) > > nit: but please group these defines by name rather than encoding. Sure, will do the same for all new register being added in the series.
diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h index b4a40535a3d8..464e828a994d 100644 --- a/arch/arm64/include/asm/cpu.h +++ b/arch/arm64/include/asm/cpu.h @@ -46,6 +46,7 @@ struct cpuinfo_arm64 { u32 reg_id_mmfr3; u32 reg_id_pfr0; u32 reg_id_pfr1; + u32 reg_id_pfr2; u32 reg_mvfr0; u32 reg_mvfr1; diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index e5317a6367b6..c977449e02db 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -153,6 +153,7 @@ #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) +#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) @@ -785,6 +786,9 @@ #define ID_ISAR6_DP_SHIFT 4 #define ID_ISAR6_JSCVT_SHIFT 0 +#define ID_PFR2_SSBS_SHIFT 4 +#define ID_PFR2_CSV3_SHIFT 0 + #define MVFR0_FPROUND_SHIFT 28 #define MVFR0_FPSHVEC_SHIFT 24 #define MVFR0_FPSQRT_SHIFT 20 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index cba43e4a5c79..a8247bf92959 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -434,6 +434,12 @@ static const struct arm64_ftr_bits ftr_id_pfr1[] = { ARM64_FTR_END, }; +static const struct arm64_ftr_bits ftr_id_pfr2[] = { + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0), + ARM64_FTR_END, +}; + static const struct arm64_ftr_bits ftr_id_dfr0[] = { S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), @@ -514,6 +520,7 @@ static const struct __ftr_reg_entry { ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), + ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), /* Op1 = 0, CRn = 0, CRm = 4 */ ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), @@ -720,6 +727,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info) init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); + init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); @@ -853,6 +861,8 @@ static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info, info->reg_id_pfr0, boot->reg_id_pfr0); taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, info->reg_id_pfr1, boot->reg_id_pfr1); + taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, + info->reg_id_pfr2, boot->reg_id_pfr2); taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, info->reg_mvfr0, boot->reg_mvfr0); taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, @@ -980,6 +990,7 @@ static u64 __read_sysreg_by_encoding(u32 sys_id) switch (sys_id) { read_sysreg_case(SYS_ID_PFR0_EL1); read_sysreg_case(SYS_ID_PFR1_EL1); + read_sysreg_case(SYS_ID_PFR2_EL1); read_sysreg_case(SYS_ID_DFR0_EL1); read_sysreg_case(SYS_ID_MMFR0_EL1); read_sysreg_case(SYS_ID_MMFR1_EL1); diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 86136075ae41..cb79b083f97f 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -375,6 +375,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1); info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1); info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1); + info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1); info->reg_mvfr0 = read_cpuid(MVFR0_EL1); info->reg_mvfr1 = read_cpuid(MVFR1_EL1); diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 51db934702b6..b784b156edb3 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1456,7 +1456,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_SANITISED(MVFR1_EL1), ID_SANITISED(MVFR2_EL1), ID_UNALLOCATED(3,3), - ID_UNALLOCATED(3,4), + ID_SANITISED(ID_PFR2_EL1), ID_UNALLOCATED(3,5), ID_UNALLOCATED(3,6), ID_UNALLOCATED(3,7),