| Message ID | 1588426445-24344-9-git-send-email-anshuman.khandual@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes | expand |
On Sat, May 02, 2020 at 07:03:57PM +0530, Anshuman Khandual wrote: > Enable all remaining feature bits like EVT, CCIDX, LSM, HPDS, CnP, XNX, > SpecSEI in ID_MMFR4 register per ARM DDI 0487F.a. > > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Suzuki K Poulose <suzuki.poulose@arm.com> > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > > Suggested-by: Mark Rutland <mark.rutland@arm.com> > Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> > --- > arch/arm64/include/asm/sysreg.h | 8 ++++++++ > arch/arm64/kernel/cpufeature.c | 13 +++++++++++++ > 2 files changed, 21 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index f9e3b9350540..0f34927f52b9 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -790,6 +790,14 @@ > #define ID_ISAR6_DP_SHIFT 4 > #define ID_ISAR6_JSCVT_SHIFT 0 > > +#define ID_MMFR4_EVT_SHIFT 28 > +#define ID_MMFR4_CCIDX_SHIFT 24 > +#define ID_MMFR4_LSM_SHIFT 20 > +#define ID_MMFR4_HPDS_SHIFT 16 > +#define ID_MMFR4_CNP_SHIFT 12 > +#define ID_MMFR4_XNX_SHIFT 8 Why didn't you add ID_MMFR4_AC2_SHIFT as well? Will
On 05/05/2020 04:44 PM, Will Deacon wrote: > On Sat, May 02, 2020 at 07:03:57PM +0530, Anshuman Khandual wrote: >> Enable all remaining feature bits like EVT, CCIDX, LSM, HPDS, CnP, XNX, >> SpecSEI in ID_MMFR4 register per ARM DDI 0487F.a. >> >> Cc: Catalin Marinas <catalin.marinas@arm.com> >> Cc: Will Deacon <will@kernel.org> >> Cc: Mark Rutland <mark.rutland@arm.com> >> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> >> Cc: linux-arm-kernel@lists.infradead.org >> Cc: linux-kernel@vger.kernel.org >> >> Suggested-by: Mark Rutland <mark.rutland@arm.com> >> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> >> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> >> --- >> arch/arm64/include/asm/sysreg.h | 8 ++++++++ >> arch/arm64/kernel/cpufeature.c | 13 +++++++++++++ >> 2 files changed, 21 insertions(+) >> >> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h >> index f9e3b9350540..0f34927f52b9 100644 >> --- a/arch/arm64/include/asm/sysreg.h >> +++ b/arch/arm64/include/asm/sysreg.h >> @@ -790,6 +790,14 @@ >> #define ID_ISAR6_DP_SHIFT 4 >> #define ID_ISAR6_JSCVT_SHIFT 0 >> >> +#define ID_MMFR4_EVT_SHIFT 28 >> +#define ID_MMFR4_CCIDX_SHIFT 24 >> +#define ID_MMFR4_LSM_SHIFT 20 >> +#define ID_MMFR4_HPDS_SHIFT 16 >> +#define ID_MMFR4_CNP_SHIFT 12 >> +#define ID_MMFR4_XNX_SHIFT 8 > > Why didn't you add ID_MMFR4_AC2_SHIFT as well? ID_MMFR4_AC2_SHIFT, which will be the replacement for an existing hard coded bits shift encoding ('4') is being added via [PATCH 16/16] where we replace all existing open encodings.
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index f9e3b9350540..0f34927f52b9 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -790,6 +790,14 @@ #define ID_ISAR6_DP_SHIFT 4 #define ID_ISAR6_JSCVT_SHIFT 0 +#define ID_MMFR4_EVT_SHIFT 28 +#define ID_MMFR4_CCIDX_SHIFT 24 +#define ID_MMFR4_LSM_SHIFT 20 +#define ID_MMFR4_HPDS_SHIFT 16 +#define ID_MMFR4_CNP_SHIFT 12 +#define ID_MMFR4_XNX_SHIFT 8 +#define ID_MMFR4_SPECSEI_SHIFT 0 + #define ID_MMFR5_ETS_SHIFT 0 #define ID_PFR0_DIT_SHIFT 24 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 4fd05a07b7a3..f4e15e355aee 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -387,7 +387,20 @@ static const struct arm64_ftr_bits ftr_id_isar5[] = { }; static const struct arm64_ftr_bits ftr_id_mmfr4[] = { + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */ + /* + * SpecSEI = 1 indicates that the PE might generate an SError on an + * external abort on speculative read. It is safe to assume that an + * SError might be generated than it will not be. Hence it has been + * classified as FTR_HIGHER_SAFE. + */ + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0), ARM64_FTR_END, };