| Message ID | 20200504225227.464666-13-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Introduce Rocket Lake | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Matt > Roper > Sent: Tuesday, May 5, 2020 4:22 AM > To: intel-gfx@lists.freedesktop.org > Cc: De Marchi, Lucas <lucas.demarchi@intel.com> > Subject: [Intel-gfx] [PATCH v2 12/22] drm/i915/rkl: Check proper SDEISR bits for > TC1 and TC2 outputs > > When Rocket Lake is paired with a TGP PCH, the last two outputs utilize the > TC1 and TC2 hpd pins, even though these are combo outputs. > > Bspec: 49181 > Cc: Lucas De Marchi <lucas.demarchi@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Looks good. Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 6952b0295096..d32bbcd99b8a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -6172,8 +6172,12 @@ static bool bxt_digital_port_connected(struct > intel_encoder *encoder) static bool intel_combo_phy_connected(struct > drm_i915_private *dev_priv, > enum phy phy) > { > - if (HAS_PCH_MCC(dev_priv) && phy == PHY_C) > - return intel_de_read(dev_priv, SDEISR) & > SDE_TC_HOTPLUG_ICP(PORT_TC1); > + if (IS_ROCKETLAKE(dev_priv) && phy >= PHY_C) > + return intel_de_read(dev_priv, SDEISR) & > + SDE_TC_HOTPLUG_ICP(phy - PHY_C); > + else if (HAS_PCH_MCC(dev_priv) && phy == PHY_C) > + return intel_de_read(dev_priv, SDEISR) & > + SDE_TC_HOTPLUG_ICP(PORT_TC1); > > return intel_de_read(dev_priv, SDEISR) & > SDE_DDI_HOTPLUG_ICP(phy); } > -- > 2.24.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Mon, May 04, 2020 at 03:52:17PM -0700, Matt Roper wrote: > When Rocket Lake is paired with a TGP PCH, the last two outputs utilize > the TC1 and TC2 hpd pins, even though these are combo outputs. > > Bspec: 49181 > Cc: Lucas De Marchi <lucas.demarchi@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 6952b0295096..d32bbcd99b8a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -6172,8 +6172,12 @@ static bool bxt_digital_port_connected(struct intel_encoder *encoder) > static bool intel_combo_phy_connected(struct drm_i915_private *dev_priv, > enum phy phy) > { > - if (HAS_PCH_MCC(dev_priv) && phy == PHY_C) > - return intel_de_read(dev_priv, SDEISR) & SDE_TC_HOTPLUG_ICP(PORT_TC1); > + if (IS_ROCKETLAKE(dev_priv) && phy >= PHY_C) > + return intel_de_read(dev_priv, SDEISR) & > + SDE_TC_HOTPLUG_ICP(phy - PHY_C); > + else if (HAS_PCH_MCC(dev_priv) && phy == PHY_C) > + return intel_de_read(dev_priv, SDEISR) & > + SDE_TC_HOTPLUG_ICP(PORT_TC1); Most of this mess is going to disappear as soon as I can land https://patchwork.freedesktop.org/series/72348/ So assuming the hpd[] thing gets correctly populated we no longer need any hack like these. > > return intel_de_read(dev_priv, SDEISR) & SDE_DDI_HOTPLUG_ICP(phy); > } > -- > 2.24.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 6952b0295096..d32bbcd99b8a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -6172,8 +6172,12 @@ static bool bxt_digital_port_connected(struct intel_encoder *encoder) static bool intel_combo_phy_connected(struct drm_i915_private *dev_priv, enum phy phy) { - if (HAS_PCH_MCC(dev_priv) && phy == PHY_C) - return intel_de_read(dev_priv, SDEISR) & SDE_TC_HOTPLUG_ICP(PORT_TC1); + if (IS_ROCKETLAKE(dev_priv) && phy >= PHY_C) + return intel_de_read(dev_priv, SDEISR) & + SDE_TC_HOTPLUG_ICP(phy - PHY_C); + else if (HAS_PCH_MCC(dev_priv) && phy == PHY_C) + return intel_de_read(dev_priv, SDEISR) & + SDE_TC_HOTPLUG_ICP(PORT_TC1); return intel_de_read(dev_priv, SDEISR) & SDE_DDI_HOTPLUG_ICP(phy); }
When Rocket Lake is paired with a TGP PCH, the last two outputs utilize the TC1 and TC2 hpd pins, even though these are combo outputs. Bspec: 49181 Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)