ARM: dts: omap3: Migrate AES from hwmods to sysc-omap2
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Message ID 20200504230100.181926-1-aford173@gmail.com
State New
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Series
  • ARM: dts: omap3: Migrate AES from hwmods to sysc-omap2
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Commit Message

Adam Ford May 4, 2020, 11:01 p.m. UTC
Various OMAP3 boards have two AES blocks, but only one is currently
available, because the hwmods are only configured for one.

This patch migrates the hwmods for the AES engine to sysc-omap2
which allows the second AES crypto engine to become available.

  omap-aes 480a6000.aes1: OMAP AES hw accel rev: 2.6
  omap-aes 480a6000.aes1: will run requests pump with realtime priority
  omap-aes 480c5000.aes2: OMAP AES hw accel rev: 2.6
  omap-aes 480c5000.aes2: will run requests pump with realtime priority

Signed-off-by: Adam Ford <aford173@gmail.com>

Comments

Tony Lindgren May 5, 2020, 6:42 p.m. UTC | #1
* Adam Ford <aford173@gmail.com> [200504 16:02]:
> Various OMAP3 boards have two AES blocks, but only one is currently
> available, because the hwmods are only configured for one.
> 
> This patch migrates the hwmods for the AES engine to sysc-omap2
> which allows the second AES crypto engine to become available.
> 
>   omap-aes 480a6000.aes1: OMAP AES hw accel rev: 2.6
>   omap-aes 480a6000.aes1: will run requests pump with realtime priority
>   omap-aes 480c5000.aes2: OMAP AES hw accel rev: 2.6
>   omap-aes 480c5000.aes2: will run requests pump with realtime priority

Great :) Looks like I'm getting the following though:

DTC     arch/arm/boot/dts/am3517-craneboard.dtb
arch/arm/boot/dts/omap3.dtsi:160.39-184.5: ERROR (phandle_references):
/ocp@68000000/target-module@480a6000:
Reference to non-existent node or label "aes1_ick"

Is this patch maybe missing a change for am3717 for the aes1_ick?

Regards,

Tony
Adam Ford May 5, 2020, 9:17 p.m. UTC | #2
On Tue, May 5, 2020 at 1:42 PM Tony Lindgren <tony@atomide.com> wrote:
>
> * Adam Ford <aford173@gmail.com> [200504 16:02]:
> > Various OMAP3 boards have two AES blocks, but only one is currently
> > available, because the hwmods are only configured for one.
> >
> > This patch migrates the hwmods for the AES engine to sysc-omap2
> > which allows the second AES crypto engine to become available.
> >
> >   omap-aes 480a6000.aes1: OMAP AES hw accel rev: 2.6
> >   omap-aes 480a6000.aes1: will run requests pump with realtime priority
> >   omap-aes 480c5000.aes2: OMAP AES hw accel rev: 2.6
> >   omap-aes 480c5000.aes2: will run requests pump with realtime priority
>
> Great :) Looks like I'm getting the following though:
>
> DTC     arch/arm/boot/dts/am3517-craneboard.dtb
> arch/arm/boot/dts/omap3.dtsi:160.39-184.5: ERROR (phandle_references):
> /ocp@68000000/target-module@480a6000:
> Reference to non-existent node or label "aes1_ick"
>
> Is this patch maybe missing a change for am3717 for the aes1_ick?

I am guessing it's the same issue that plagues the am3517 with a note
in the hwmods that stated noone seems to know which am3517's support
it and which don't.  The RNG was disabled on the 3517, so I am
guessing I'll do the same for AES.
I should have posted it as an RFC, because I don't have the proper IRQ
setup for the newly supported AES engine.  The interrupts that are
used for the original AES are listed as 'Resereved' in the AM3517 TRM.
I assume the second engine uses different interrupts.  I don't suppose
anyone know what it should be?

adam
>
> Regards,
>
> Tony
Tony Lindgren May 5, 2020, 11:34 p.m. UTC | #3
* Adam Ford <aford173@gmail.com> [200505 21:18]:
> On Tue, May 5, 2020 at 1:42 PM Tony Lindgren <tony@atomide.com> wrote:
> >
> > * Adam Ford <aford173@gmail.com> [200504 16:02]:
> > > Various OMAP3 boards have two AES blocks, but only one is currently
> > > available, because the hwmods are only configured for one.
> > >
> > > This patch migrates the hwmods for the AES engine to sysc-omap2
> > > which allows the second AES crypto engine to become available.
> > >
> > >   omap-aes 480a6000.aes1: OMAP AES hw accel rev: 2.6
> > >   omap-aes 480a6000.aes1: will run requests pump with realtime priority
> > >   omap-aes 480c5000.aes2: OMAP AES hw accel rev: 2.6
> > >   omap-aes 480c5000.aes2: will run requests pump with realtime priority
> >
> > Great :) Looks like I'm getting the following though:
> >
> > DTC     arch/arm/boot/dts/am3517-craneboard.dtb
> > arch/arm/boot/dts/omap3.dtsi:160.39-184.5: ERROR (phandle_references):
> > /ocp@68000000/target-module@480a6000:
> > Reference to non-existent node or label "aes1_ick"
> >
> > Is this patch maybe missing a change for am3717 for the aes1_ick?
> 
> I am guessing it's the same issue that plagues the am3517 with a note
> in the hwmods that stated noone seems to know which am3517's support
> it and which don't.  The RNG was disabled on the 3517, so I am
> guessing I'll do the same for AES.

OK, I have no idea what modules might be there on am3517.

> I should have posted it as an RFC, because I don't have the proper IRQ
> setup for the newly supported AES engine.  The interrupts that are
> used for the original AES are listed as 'Resereved' in the AM3517 TRM.
> I assume the second engine uses different interrupts.  I don't suppose
> anyone know what it should be?

Sorry no idea, usually the secure accelerator documentation is just
left out it seems. My guess the values are the same as on omap3.

Regards,

Tony
Adam Ford June 13, 2020, 11:10 a.m. UTC | #4
On Tue, May 5, 2020 at 6:34 PM Tony Lindgren <tony@atomide.com> wrote:
>
> * Adam Ford <aford173@gmail.com> [200505 21:18]:
> > On Tue, May 5, 2020 at 1:42 PM Tony Lindgren <tony@atomide.com> wrote:
> > >
> > > * Adam Ford <aford173@gmail.com> [200504 16:02]:
> > > > Various OMAP3 boards have two AES blocks, but only one is currently
> > > > available, because the hwmods are only configured for one.
> > > >
> > > > This patch migrates the hwmods for the AES engine to sysc-omap2
> > > > which allows the second AES crypto engine to become available.
> > > >
> > > >   omap-aes 480a6000.aes1: OMAP AES hw accel rev: 2.6
> > > >   omap-aes 480a6000.aes1: will run requests pump with realtime priority
> > > >   omap-aes 480c5000.aes2: OMAP AES hw accel rev: 2.6
> > > >   omap-aes 480c5000.aes2: will run requests pump with realtime priority
> > >
> > > Great :) Looks like I'm getting the following though:
> > >
> > > DTC     arch/arm/boot/dts/am3517-craneboard.dtb
> > > arch/arm/boot/dts/omap3.dtsi:160.39-184.5: ERROR (phandle_references):
> > > /ocp@68000000/target-module@480a6000:
> > > Reference to non-existent node or label "aes1_ick"
> > >
> > > Is this patch maybe missing a change for am3717 for the aes1_ick?
> >
> > I am guessing it's the same issue that plagues the am3517 with a note
> > in the hwmods that stated noone seems to know which am3517's support
> > it and which don't.  The RNG was disabled on the 3517, so I am
> > guessing I'll do the same for AES.
>
> OK, I have no idea what modules might be there on am3517.

I'm going to repost a V2 with the node removed on am3517.

>
> > I should have posted it as an RFC, because I don't have the proper IRQ
> > setup for the newly supported AES engine.  The interrupts that are
> > used for the original AES are listed as 'Reserved' in the AM3517 TRM.

Through trial and error, I think I have the right IRQ for OMAP3630 for
the 2nd instance.

> > I assume the second engine uses different interrupts.  I don't suppose
> > anyone know what it should be?
>
> Sorry no idea, usually the secure accelerator documentation is just
> left out it seems. My guess the values are the same as on omap3.

Tony - Could you review the hwmod transition I did for the first
engine to make sure I did it right?

If you think I did it right, I'll post my V2.

adam
>
> Regards,
>
> Tony
Tony Lindgren June 13, 2020, 3:50 p.m. UTC | #5
* Adam Ford <aford173@gmail.com> [200613 11:11]:
> Through trial and error, I think I have the right IRQ for OMAP3630 for
> the 2nd instance.

OK great.

> > > I assume the second engine uses different interrupts.  I don't suppose
> > > anyone know what it should be?
> >
> > Sorry no idea, usually the secure accelerator documentation is just
> > left out it seems. My guess the values are the same as on omap3.
> 
> Tony - Could you review the hwmod transition I did for the first
> engine to make sure I did it right?

Yeah that's about all there is to it :)

> If you think I did it right, I'll post my V2.

Yes please do.

Regards,

Tony

Patch
diff mbox series

diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index adcdf88717a3..376628b32f77 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -157,13 +157,56 @@  omap3_pmx_wkup: pinmux@a00 {
 			};
 		};
 
-		aes: aes@480c5000 {
-			compatible = "ti,omap3-aes";
-			ti,hwmods = "aes";
-			reg = <0x480c5000 0x50>;
-			interrupts = <0>;
-			dmas = <&sdma 65 &sdma 66>;
-			dma-names = "tx", "rx";
+		aes1_target: target-module@480a6000 {
+			compatible = "ti,sysc-omap2", "ti,sysc";
+			reg = <0x480a6044 0x4>,
+			      <0x480a6048 0x4>,
+			      <0x480a604c 0x4>;
+			reg-names = "rev", "sysc", "syss";
+			ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
+			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+					<SYSC_IDLE_NO>,
+					<SYSC_IDLE_SMART>;
+			ti,syss-mask = <1>;
+			clocks = <&aes1_ick>;
+			clock-names = "ick";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x480a6000 0x2000>;
+
+			aes1: aes1@0 {
+				compatible = "ti,omap3-aes";
+				reg = <0 0x50>;
+				interrupts = <0>;
+				dmas = <&sdma 65 &sdma 66>;
+				dma-names = "tx", "rx";
+			};
+		};
+
+		aes2_target: target-module@480c5000 {
+			compatible = "ti,sysc-omap2", "ti,sysc";
+			reg = <0x480c5044 0x4>,
+			      <0x480c5048 0x4>,
+			      <0x480c504c 0x4>;
+			reg-names = "rev", "sysc", "syss";
+			ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
+			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+					<SYSC_IDLE_NO>,
+					<SYSC_IDLE_SMART>;
+			ti,syss-mask = <1>;
+			clocks = <&aes2_ick>;
+			clock-names = "ick";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x480c5000 0x2000>;
+
+			aes2: aes2@0 {
+				compatible = "ti,omap3-aes";
+				reg = <0 0x50>;
+				interrupts = <0>;
+				dmas = <&sdma 65 &sdma 66>;
+				dma-names = "tx", "rx";
+			};
 		};
 
 		prm: prm@48306000 {
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index ca02f91237e3..b6c7d98a9eff 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -2342,44 +2342,6 @@  static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4_core -> AES */
-static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
-	.rev_offs	= 0x44,
-	.sysc_offs	= 0x48,
-	.syss_offs	= 0x4c,
-	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
-			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-	.sysc_fields	= &omap3xxx_aes_sysc_fields,
-};
-
-static struct omap_hwmod_class omap3xxx_aes_class = {
-	.name	= "aes",
-	.sysc	= &omap3_aes_sysc,
-};
-
-
-static struct omap_hwmod omap3xxx_aes_hwmod = {
-	.name		= "aes",
-	.main_clk	= "aes2_ick",
-	.prcm		= {
-		.omap2 = {
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
-		},
-	},
-	.class		= &omap3xxx_aes_class,
-};
-
-
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
-	.master		= &omap3xxx_l4_core_hwmod,
-	.slave		= &omap3xxx_aes_hwmod,
-	.clk		= "aes2_ick",
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /*
  * 'ssi' class
  * synchronous serial interface (multichannel and full-duplex serial if)
@@ -2473,20 +2435,11 @@  static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
 	NULL,
 };
 
-static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
-	&omap3xxx_l4_core__aes,
-	NULL,
-};
-
 static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
 	&omap3xxx_l4_core__sham,
 	NULL
 };
 
-static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = {
-	&omap3xxx_l4_core__aes,
-	NULL
-};
 
 /*
  * Apparently the SHA/MD5 and AES accelerator IP blocks are
@@ -2501,11 +2454,6 @@  static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
 	NULL
 };
 
-static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
-	/* &omap3xxx_l4_core__aes, */
-	NULL,
-};
-
 /* 3430ES1-only hwmod links */
 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
 	&omap3430es1_dss__l3,
@@ -2641,7 +2589,6 @@  int __init omap3xxx_hwmod_init(void)
 {
 	int r;
 	struct omap_hwmod_ocp_if **h = NULL, **h_sham = NULL;
-	struct omap_hwmod_ocp_if **h_aes = NULL;
 	struct device_node *bus;
 	unsigned int rev;
 
@@ -2664,16 +2611,13 @@  int __init omap3xxx_hwmod_init(void)
 	    rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
 		h = omap34xx_hwmod_ocp_ifs;
 		h_sham = omap34xx_sham_hwmod_ocp_ifs;
-		h_aes = omap34xx_aes_hwmod_ocp_ifs;
 	} else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
 		h = am35xx_hwmod_ocp_ifs;
 		h_sham = am35xx_sham_hwmod_ocp_ifs;
-		h_aes = am35xx_aes_hwmod_ocp_ifs;
 	} else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
 		   rev == OMAP3630_REV_ES1_2) {
 		h = omap36xx_hwmod_ocp_ifs;
 		h_sham = omap36xx_sham_hwmod_ocp_ifs;
-		h_aes = omap36xx_aes_hwmod_ocp_ifs;
 	} else {
 		WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
 		return -EINVAL;
@@ -2696,11 +2640,6 @@  int __init omap3xxx_hwmod_init(void)
 			goto put_node;
 	}
 
-	if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
-		r = omap_hwmod_register_links(h_aes);
-		if (r < 0)
-			goto put_node;
-	}
 	of_node_put(bus);
 
 	/*