| Message ID | 20200507144503.15506-2-stanislav.lisovskiy@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | SAGV support for Gen12+ | expand |
On Thu, May 07, 2020 at 05:44:58PM +0300, Stanislav Lisovskiy wrote: > For future Gen12 SAGV implementation we need to > seemlessly alter wm levels calculated, depending > on whether we are allowed to enable SAGV or not. > > So this accessor will give additional flexibility > to do that. > > Currently this accessor is still simply working > as "pass-through" function. This will be changed > in next coming patches from this series. > > v2: - plane_id -> plane->id(Ville Syrjälä) > - Moved wm_level var to have more local scope > (Ville Syrjälä) > - Renamed yuv to color_plane(Ville Syrjälä) in > skl_plane_wm_level > > v3: - plane->id -> plane_id(this time for real, Ville Syrjälä) > - Changed colorplane id type from boolean to int as index > (Ville Syrjälä) > - Moved crtc_state param so that it is first now > (Ville Syrjälä) > - Moved wm_level declaration to tigher scope in > skl_write_plane_wm(Ville Syrjälä) > > v4: - Started to use enum values for color plane > - Do sizeof for a type what we are memset'ing > - Zero out wm_uv as well(Ville Syrjälä) > > v5: - Fixed rebase conflict caused by COLOR_PLANE_* > enum removal > > v6: - Do not use skl_plane_wm_level accessor in skl_allocate_pipe_ddb > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 26 ++++++++++++++++++++++++-- > 1 file changed, 24 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 416cb1a1e7cb..8a86298962dc 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4632,6 +4632,18 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state, > return total_data_rate; > } > > +static const struct skl_wm_level * > +skl_plane_wm_level(const struct intel_crtc_state *crtc_state, > + enum plane_id plane_id, > + int level, > + int color_plane) > +{ > + const struct skl_plane_wm *wm = > + &crtc_state->wm.skl.optimal.planes[plane_id]; > + > + return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level]; uv_wm still not a thing as far as the hw is concerned, so can't see why we'd have this here. > +} > + > static int > skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state) > { > @@ -5439,8 +5451,13 @@ void skl_write_plane_wm(struct intel_plane *plane, > &crtc_state->wm.skl.plane_ddb_uv[plane_id]; > > for (level = 0; level <= max_level; level++) { > + const struct skl_wm_level *wm_level; > + int color_plane = 0; > + > + wm_level = skl_plane_wm_level(crtc_state, plane_id, level, color_plane); > + > skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level), > - &wm->wm[level]); > + wm_level); > } > skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id), > &wm->trans_wm); > @@ -5473,8 +5490,13 @@ void skl_write_cursor_wm(struct intel_plane *plane, > &crtc_state->wm.skl.plane_ddb_y[plane_id]; > > for (level = 0; level <= max_level; level++) { > + const struct skl_wm_level *wm_level; > + int color_plane = 0; > + > + wm_level = skl_plane_wm_level(crtc_state, plane_id, level, color_plane); > + > skl_write_wm_level(dev_priv, CUR_WM(pipe, level), > - &wm->wm[level]); > + wm_level); > } > skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm); > > -- > 2.24.1.485.gad05a3d8e5
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 416cb1a1e7cb..8a86298962dc 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4632,6 +4632,18 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state, return total_data_rate; } +static const struct skl_wm_level * +skl_plane_wm_level(const struct intel_crtc_state *crtc_state, + enum plane_id plane_id, + int level, + int color_plane) +{ + const struct skl_plane_wm *wm = + &crtc_state->wm.skl.optimal.planes[plane_id]; + + return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level]; +} + static int skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state) { @@ -5439,8 +5451,13 @@ void skl_write_plane_wm(struct intel_plane *plane, &crtc_state->wm.skl.plane_ddb_uv[plane_id]; for (level = 0; level <= max_level; level++) { + const struct skl_wm_level *wm_level; + int color_plane = 0; + + wm_level = skl_plane_wm_level(crtc_state, plane_id, level, color_plane); + skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level), - &wm->wm[level]); + wm_level); } skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id), &wm->trans_wm); @@ -5473,8 +5490,13 @@ void skl_write_cursor_wm(struct intel_plane *plane, &crtc_state->wm.skl.plane_ddb_y[plane_id]; for (level = 0; level <= max_level; level++) { + const struct skl_wm_level *wm_level; + int color_plane = 0; + + wm_level = skl_plane_wm_level(crtc_state, plane_id, level, color_plane); + skl_write_wm_level(dev_priv, CUR_WM(pipe, level), - &wm->wm[level]); + wm_level); } skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
For future Gen12 SAGV implementation we need to seemlessly alter wm levels calculated, depending on whether we are allowed to enable SAGV or not. So this accessor will give additional flexibility to do that. Currently this accessor is still simply working as "pass-through" function. This will be changed in next coming patches from this series. v2: - plane_id -> plane->id(Ville Syrjälä) - Moved wm_level var to have more local scope (Ville Syrjälä) - Renamed yuv to color_plane(Ville Syrjälä) in skl_plane_wm_level v3: - plane->id -> plane_id(this time for real, Ville Syrjälä) - Changed colorplane id type from boolean to int as index (Ville Syrjälä) - Moved crtc_state param so that it is first now (Ville Syrjälä) - Moved wm_level declaration to tigher scope in skl_write_plane_wm(Ville Syrjälä) v4: - Started to use enum values for color plane - Do sizeof for a type what we are memset'ing - Zero out wm_uv as well(Ville Syrjälä) v5: - Fixed rebase conflict caused by COLOR_PLANE_* enum removal v6: - Do not use skl_plane_wm_level accessor in skl_allocate_pipe_ddb Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-)