[GIT,PULL] clk: meson: updates for v5.8
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  • [GIT,PULL] clk: meson: updates for v5.8
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Pull-request

git://github.com/BayLibre/clk-meson.git tags/clk-meson-v5.8-1

Message

Jerome Brunet May 11, 2020, 9:28 a.m. UTC
Hi Stephen,

Here are the amlogic clock updates for v5.8.
Nothing fancy, please pull.

Cheers

The following changes since commit 8f3d9f354286745c751374f5f1fcafee6b3f3136:

  Linux 5.7-rc1 (2020-04-12 12:35:55 -0700)

are available in the Git repository at:

  git://github.com/BayLibre/clk-meson.git tags/clk-meson-v5.8-1

for you to fetch changes up to a29ae8600d50ece1856b062a39ed296b8b952259:

  clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers (2020-05-02 01:53:32 +0200)

----------------------------------------------------------------
Amlogic clock updates for v5.8:

* Meson8b: Updates and fixup HDMI and video clocks
* Meson8b: Fixup reset polarity
* Meson gx and g12: fix GPU glitch free mux switch

----------------------------------------------------------------
Martin Blumenstingl (9):
      clk: meson8b: export the HDMI system clock
      clk: meson: meson8b: make the hdmi_sys clock tree mutable
      clk: meson: gxbb: Prepare the GPU clock tree to change at runtime
      clk: meson: g12a: Prepare the GPU clock tree to change at runtime
      clk: meson: meson8b: Fix the first parent of vid_pll_in_sel
      clk: meson: meson8b: Fix the polarity of the RESET_N lines
      clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bits
      clk: meson: meson8b: Make the CCF use the glitch-free VPU mux
      clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers

 drivers/clk/meson/g12a.c                 |  30 +++++---
 drivers/clk/meson/gxbb.c                 |  40 ++++++-----
 drivers/clk/meson/meson8b.c              | 120 ++++++++++++++++++++++---------
 drivers/clk/meson/meson8b.h              |   5 +-
 include/dt-bindings/clock/meson8b-clkc.h |   1 +
 5 files changed, 134 insertions(+), 62 deletions(-)

Comments

Stephen Boyd May 14, 2020, 8:38 p.m. UTC | #1
Quoting Jerome Brunet (2020-05-11 02:28:45)
> Hi Stephen,
> 
> Here are the amlogic clock updates for v5.8.
> Nothing fancy, please pull.
> 
> Cheers
> 
> The following changes since commit 8f3d9f354286745c751374f5f1fcafee6b3f3136:
> 
>   Linux 5.7-rc1 (2020-04-12 12:35:55 -0700)
> 
> are available in the Git repository at:
> 
>   git://github.com/BayLibre/clk-meson.git tags/clk-meson-v5.8-1
> 
> for you to fetch changes up to a29ae8600d50ece1856b062a39ed296b8b952259:
> 
>   clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers (2020-05-02 01:53:32 +0200)
> 
> ----------------------------------------------------------------

Thanks. Pulled into clk-next
Stephen Boyd May 14, 2020, 8:55 p.m. UTC | #2
Quoting Jerome Brunet (2020-05-11 02:28:45)
> Hi Stephen,
> 
> Here are the amlogic clock updates for v5.8.
> Nothing fancy, please pull.
> 
> Cheers
> 
> The following changes since commit 8f3d9f354286745c751374f5f1fcafee6b3f3136:
> 
>   Linux 5.7-rc1 (2020-04-12 12:35:55 -0700)
> 
> are available in the Git repository at:
> 
>   git://github.com/BayLibre/clk-meson.git tags/clk-meson-v5.8-1
> 
> for you to fetch changes up to a29ae8600d50ece1856b062a39ed296b8b952259:
> 
>   clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers (2020-05-02 01:53:32 +0200)
> 
> ----------------------------------------------------------------
> Amlogic clock updates for v5.8:
> 
> * Meson8b: Updates and fixup HDMI and video clocks
> * Meson8b: Fixup reset polarity
> * Meson gx and g12: fix GPU glitch free mux switch
> 
> ----------------------------------------------------------------

Should also mention that sparse on arm64 complains about 

drivers/clk/meson/g12a.c:5074:43: warning: invalid access past the end of 'g12b_hw_onecell_data' (1472 8)

but I have no idea if that's a real problem. Maybe my sparse build is
bad?
Jerome Brunet May 14, 2020, 9:42 p.m. UTC | #3
On Thu 14 May 2020 at 22:55, Stephen Boyd <sboyd@kernel.org> wrote:

> Quoting Jerome Brunet (2020-05-11 02:28:45)
>> Hi Stephen,
>> 
>> Here are the amlogic clock updates for v5.8.
>> Nothing fancy, please pull.
>> 
>> Cheers
>> 
>> The following changes since commit 8f3d9f354286745c751374f5f1fcafee6b3f3136:
>> 
>>   Linux 5.7-rc1 (2020-04-12 12:35:55 -0700)
>> 
>> are available in the Git repository at:
>> 
>>   git://github.com/BayLibre/clk-meson.git tags/clk-meson-v5.8-1
>> 
>> for you to fetch changes up to a29ae8600d50ece1856b062a39ed296b8b952259:
>> 
>>   clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers (2020-05-02 01:53:32 +0200)
>> 
>> ----------------------------------------------------------------
>> Amlogic clock updates for v5.8:
>> 
>> * Meson8b: Updates and fixup HDMI and video clocks
>> * Meson8b: Fixup reset polarity
>> * Meson gx and g12: fix GPU glitch free mux switch
>> 
>> ----------------------------------------------------------------
>
> Should also mention that sparse on arm64 complains about 
>
> drivers/clk/meson/g12a.c:5074:43: warning: invalid access past the end of 'g12b_hw_onecell_data' (1472 8)
>
> but I have no idea if that's a real problem. Maybe my sparse build is
> bad?

This is weird. IIUC, it complains about

> xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);

CLKID_CPU_CLK_DYN1_SEL id is 183
and we make sure that the table is always NR_CLKS long. In the g12a case
it's 262.