diff mbox series

[v7,4/7] drm/i915: Plane configuration affects CDCLK in Gen11+

Message ID 20200511150545.15149-5-stanislav.lisovskiy@intel.com (mailing list archive)
State New, archived
Headers show
Series Consider DBuf bandwidth when calculating CDCLK | expand

Commit Message

Lisovskiy, Stanislav May 11, 2020, 3:05 p.m. UTC 
From: Stanislav Lisovskiy <stanislav.lisovskiY@intel.com>

So lets support it.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7e00a07e0d7a..012c3ed64b02 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14569,7 +14569,7 @@  static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
 	/* See {hsw,vlv,ivb}_plane_ratio() */
 	return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
 		IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
-		IS_IVYBRIDGE(dev_priv);
+		IS_IVYBRIDGE(dev_priv) || (INTEL_GEN(dev_priv) >= 11);
 }
 
 static int intel_atomic_check_planes(struct intel_atomic_state *state)