| Message ID | 1589360614-1164-1-git-send-email-anshuman.khandual@arm.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | f73531f0257f6bac44a8c9d5c2f3a3ccaea3d1e9 |
| Headers | show |
| Series | [V2] arm64/cpufeature: Drop open encodings while extracting parange | expand |
On Wed, May 13, 2020 at 02:33:34PM +0530, Anshuman Khandual wrote: > Currently there are multiple instances of parange feature width mask open > encodings while fetching it's value. Even the width mask value (0x7) itself > is not accurate. It should be (0xf) per ID_AA64MMFR0_EL1.PARange[3:0] as in > ARM ARM (0487F.a). Replace them with cpuid_feature_extract_unsigned_field() > which can extract given standard feature (4 bits width i.e 0xf mask) field. > > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Marc Zyngier <maz@kernel.org> > Cc: James Morse <james.morse@arm.com> > Cc: kvmarm@lists.cs.columbia.edu > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> > --- > Changes in V2: > > - Used cpuid_feature_extract_unsigned_field() per Mark > > Changes in V1: (https://patchwork.kernel.org/patch/11541913/) > > arch/arm64/kernel/cpufeature.c | 3 ++- > arch/arm64/kvm/reset.c | 11 ++++++++--- > 2 files changed, 10 insertions(+), 4 deletions(-) Acked-by: Will Deacon <will@kernel.org> I'm assuming Marc will take this, but let me know if it should go via arm64 instead (where we have a bunch of other cpufeature stuff queued). Will
On Mon, May 18, 2020 at 05:59:59PM +0100, Will Deacon wrote: > On Wed, May 13, 2020 at 02:33:34PM +0530, Anshuman Khandual wrote: > > Currently there are multiple instances of parange feature width mask open > > encodings while fetching it's value. Even the width mask value (0x7) itself > > is not accurate. It should be (0xf) per ID_AA64MMFR0_EL1.PARange[3:0] as in > > ARM ARM (0487F.a). Replace them with cpuid_feature_extract_unsigned_field() > > which can extract given standard feature (4 bits width i.e 0xf mask) field. > > > > Cc: Catalin Marinas <catalin.marinas@arm.com> > > Cc: Will Deacon <will@kernel.org> > > Cc: Marc Zyngier <maz@kernel.org> > > Cc: James Morse <james.morse@arm.com> > > Cc: kvmarm@lists.cs.columbia.edu > > Cc: linux-arm-kernel@lists.infradead.org > > Cc: linux-kernel@vger.kernel.org > > > > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> > > --- > > Changes in V2: > > > > - Used cpuid_feature_extract_unsigned_field() per Mark > > > > Changes in V1: (https://patchwork.kernel.org/patch/11541913/) > > > > arch/arm64/kernel/cpufeature.c | 3 ++- > > arch/arm64/kvm/reset.c | 11 ++++++++--- > > 2 files changed, 10 insertions(+), 4 deletions(-) > > Acked-by: Will Deacon <will@kernel.org> > > I'm assuming Marc will take this, but let me know if it should go via arm64 > instead (where we have a bunch of other cpufeature stuff queued). Hmm, but having just spotted [1], it looks like we might need a bit of co-ordination here. Marc? Will [1] https://lore.kernel.org/r/1589248647-22925-1-git-send-email-anshuman.khandual@arm.com
On Mon, 18 May 2020 18:09:34 +0100, Will Deacon <will@kernel.org> wrote: > > On Mon, May 18, 2020 at 05:59:59PM +0100, Will Deacon wrote: > > On Wed, May 13, 2020 at 02:33:34PM +0530, Anshuman Khandual wrote: > > > Currently there are multiple instances of parange feature width mask open > > > encodings while fetching it's value. Even the width mask value (0x7) itself > > > is not accurate. It should be (0xf) per ID_AA64MMFR0_EL1.PARange[3:0] as in > > > ARM ARM (0487F.a). Replace them with cpuid_feature_extract_unsigned_field() > > > which can extract given standard feature (4 bits width i.e 0xf mask) field. > > > > > > Cc: Catalin Marinas <catalin.marinas@arm.com> > > > Cc: Will Deacon <will@kernel.org> > > > Cc: Marc Zyngier <maz@kernel.org> > > > Cc: James Morse <james.morse@arm.com> > > > Cc: kvmarm@lists.cs.columbia.edu > > > Cc: linux-arm-kernel@lists.infradead.org > > > Cc: linux-kernel@vger.kernel.org > > > > > > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> > > > --- > > > Changes in V2: > > > > > > - Used cpuid_feature_extract_unsigned_field() per Mark > > > > > > Changes in V1: (https://patchwork.kernel.org/patch/11541913/) > > > > > > arch/arm64/kernel/cpufeature.c | 3 ++- > > > arch/arm64/kvm/reset.c | 11 ++++++++--- > > > 2 files changed, 10 insertions(+), 4 deletions(-) > > > > Acked-by: Will Deacon <will@kernel.org> > > > > I'm assuming Marc will take this, but let me know if it should go via arm64 > > instead (where we have a bunch of other cpufeature stuff queued). > > Hmm, but having just spotted [1], it looks like we might need a bit of > co-ordination here. Marc? Yeah, there is a clear dependency between the two. I'm happy to take both patches via the KVM tree, or to have a shared branch with the arm64 tree (we already have one for Andrew's generic AT patch). Just let me know, M.
On Wed, 13 May 2020 14:33:34 +0530 Anshuman Khandual <anshuman.khandual@arm.com> wrote: > Currently there are multiple instances of parange feature width mask open > encodings while fetching it's value. Even the width mask value (0x7) itself > is not accurate. It should be (0xf) per ID_AA64MMFR0_EL1.PARange[3:0] as in > ARM ARM (0487F.a). Replace them with cpuid_feature_extract_unsigned_field() > which can extract given standard feature (4 bits width i.e 0xf mask) field. > > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Marc Zyngier <maz@kernel.org> > Cc: James Morse <james.morse@arm.com> > Cc: kvmarm@lists.cs.columbia.edu > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Acked-by: Marc Zyngier <maz@kernel.org> M.
On Wed, 13 May 2020 14:33:34 +0530, Anshuman Khandual wrote: > Currently there are multiple instances of parange feature width mask open > encodings while fetching it's value. Even the width mask value (0x7) itself > is not accurate. It should be (0xf) per ID_AA64MMFR0_EL1.PARange[3:0] as in > ARM ARM (0487F.a). Replace them with cpuid_feature_extract_unsigned_field() > which can extract given standard feature (4 bits width i.e 0xf mask) field. > > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Marc Zyngier <maz@kernel.org> > Cc: James Morse <james.morse@arm.com> > Cc: kvmarm@lists.cs.columbia.edu > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org Applied to arm64 (for-next/cpufeature), thanks! [1/1] arm64/cpufeature: Drop open encodings while extracting parange https://git.kernel.org/arm64/c/f73531f0257f Cheers,
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 30917fe7942a..958a96947c2c 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2201,7 +2201,8 @@ void verify_hyp_capabilities(void) } /* Verify IPA range */ - parange = mmfr0 & 0x7; + parange = cpuid_feature_extract_unsigned_field(mmfr0, + ID_AA64MMFR0_PARANGE_SHIFT); ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); if (ipa_max < get_kvm_ipa_limit()) { pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index 841b492ff334..bd9f66a81e1e 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -348,8 +348,11 @@ u32 get_kvm_ipa_limit(void) void kvm_set_ipa_limit(void) { unsigned int ipa_max, pa_max, va_max, parange; + u64 mmfr0; - parange = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1) & 0x7; + mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); + parange = cpuid_feature_extract_unsigned_field(mmfr0, + ID_AA64MMFR0_PARANGE_SHIFT); pa_max = id_aa64mmfr0_parange_to_phys_shift(parange); /* Clamp the IPA limit to the PA size supported by the kernel */ @@ -395,7 +398,7 @@ void kvm_set_ipa_limit(void) */ int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type) { - u64 vtcr = VTCR_EL2_FLAGS; + u64 vtcr = VTCR_EL2_FLAGS, mmfr0; u32 parange, phys_shift; u8 lvls; @@ -411,7 +414,9 @@ int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type) phys_shift = KVM_PHYS_SHIFT; } - parange = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1) & 7; + mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); + parange = cpuid_feature_extract_unsigned_field(mmfr0, + ID_AA64MMFR0_PARANGE_SHIFT); if (parange > ID_AA64MMFR0_PARANGE_MAX) parange = ID_AA64MMFR0_PARANGE_MAX; vtcr |= parange << VTCR_EL2_PS_SHIFT;
Currently there are multiple instances of parange feature width mask open encodings while fetching it's value. Even the width mask value (0x7) itself is not accurate. It should be (0xf) per ID_AA64MMFR0_EL1.PARange[3:0] as in ARM ARM (0487F.a). Replace them with cpuid_feature_extract_unsigned_field() which can extract given standard feature (4 bits width i.e 0xf mask) field. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Marc Zyngier <maz@kernel.org> Cc: James Morse <james.morse@arm.com> Cc: kvmarm@lists.cs.columbia.edu Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> --- Changes in V2: - Used cpuid_feature_extract_unsigned_field() per Mark Changes in V1: (https://patchwork.kernel.org/patch/11541913/) arch/arm64/kernel/cpufeature.c | 3 ++- arch/arm64/kvm/reset.c | 11 ++++++++--- 2 files changed, 10 insertions(+), 4 deletions(-)