Message ID | 20200514123838.3017-2-ville.syrjala@linux.intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [v2,1/3] drm/i915: Fix 400 MHz FSB readout on elk | expand |
Quoting Ville Syrjala (2020-05-14 13:38:37) > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Document the fact that we aren't reading out the actual FSB > frequency but rather just the state of the FSB straps. > Some BIOSen allow you to configure the two independently. > So if someone sets the two up in an inconsistent manner > we'll get the wrong answer here and thus will end up with > incorrect aux/pps clock dividers. Alas, proper docs are no > longer around so we can't do any better. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index c17cf611625c..d57dfec7e9a5 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2704,7 +2704,16 @@ static int g4x_hrawclk(struct drm_i915_private *dev_priv) { u32 clkcfg; - /* hrawclock is 1/4 the FSB frequency */ + /* + * hrawclock is 1/4 the FSB frequency + * + * Note that this only reads the state of the FSB + * straps, not the actual FSB frequency. Some BIOSen + * let you configure each independently. Ideally we'd + * read out the actual FSB frequency but sadly we + * don't know which registers have that information, + * and all the relevant docs have gone to bit heaven :( + */ clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK; /* ELK seems to redefine some of the values */