From patchwork Thu May 21 00:37:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 11561911 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1B074138A for ; Thu, 21 May 2020 00:38:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 04759207D3 for ; Thu, 21 May 2020 00:38:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 04759207D3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4AA566E8E1; Thu, 21 May 2020 00:38:36 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id CB4F46E8CD for ; Thu, 21 May 2020 00:38:12 +0000 (UTC) IronPort-SDR: dJf1fB4tsOY5dvSTgsfYTx3gSWoJ/4FqCKbgEqu5mjCq45F1R1eOUXv81tZgr1Uyv+pO4IFxea 2WoVWBmaXWfg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2020 17:38:12 -0700 IronPort-SDR: wj6T7aXC6aYs8YsGkVhAwUkWucz/UXM+q4yjJY09HyTK0JUS4Cfz0vZsUPHT1qhG/Vir14g3KL o2WbOpQy3i3g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,415,1583222400"; d="scan'208";a="466720931" Received: from ldmartin1-desk.jf.intel.com ([10.165.21.151]) by fmsmga006.fm.intel.com with ESMTP; 20 May 2020 17:38:12 -0700 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Wed, 20 May 2020 17:37:50 -0700 Message-Id: <20200521003803.18936-25-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200521003803.18936-1-lucas.demarchi@intel.com> References: <20200521003803.18936-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 24/37] drm/i915/dg1: invert HPD pins X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fernando.pacheco@intel.com, Matthew Auld Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Clinton A Taylor HPD pins are inverted for DG1 platform. Bspec: 49956 Cc: José Roberto de Souza Cc: Matt Roper Signed-off-by: Clinton A Taylor Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/i915_irq.c | 4 ++++ drivers/gpu/drm/i915/i915_reg.h | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index df82d8aa1a27..ebc80e8b1599 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3177,6 +3177,10 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv) static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv) { + intel_de_rmw(dev_priv, SOUTH_CHICKEN1, 0, + INVERT_DDIA_HPD | INVERT_DDIB_HPD | + INVERT_DDIC_HPD | INVERT_DDID_HPD); + icp_hpd_irq_setup(dev_priv, SDE_DDI_MASK_DG1, 0, DG1_DDI_HPD_ENABLE_MASK, 0); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a9d7b93d79ce..e0bd9e02c3d1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8599,6 +8599,10 @@ enum { #define SOUTH_CHICKEN1 _MMIO(0xc2000) #define FDIA_PHASE_SYNC_SHIFT_OVR 19 #define FDIA_PHASE_SYNC_SHIFT_EN 18 +#define INVERT_DDID_HPD (1 << 18) +#define INVERT_DDIC_HPD (1 << 17) +#define INVERT_DDIB_HPD (1 << 16) +#define INVERT_DDIA_HPD (1 << 15) #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) #define FDI_BC_BIFURCATION_SELECT (1 << 12)