| Message ID | 20200521092258.82503-1-roger.pau@citrix.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v4] x86/idle: prevent entering C6 with in service interrupts on Intel | expand |
On 21.05.2020 11:22, Roger Pau Monne wrote: > Apply a workaround for Intel errata BDX99, CLX30, SKX100, CFW125, > BDF104, BDH85, BDM135, KWB131: "A Pending Fixed Interrupt May Be > Dispatched Before an Interrupt of The Same Priority Completes". While the change looks good to me as far as Broadwell goes, I think it was before this posting that Andrew also pointed at a specific Haswell erratum instance, still on the v3 thread. Am I to imply a v5 will follow adding affected Haswell models to the table? Jan
On Fri, May 22, 2020 at 03:42:10PM +0200, Jan Beulich wrote: > On 21.05.2020 11:22, Roger Pau Monne wrote: > > Apply a workaround for Intel errata BDX99, CLX30, SKX100, CFW125, > > BDF104, BDH85, BDM135, KWB131: "A Pending Fixed Interrupt May Be > > Dispatched Before an Interrupt of The Same Priority Completes". > > While the change looks good to me as far as Broadwell goes, I > think it was before this posting that Andrew also pointed at > a specific Haswell erratum instance, still on the v3 thread. > Am I to imply a v5 will follow adding affected Haswell models > to the table? Those refer to a different errata, see: https://lore.kernel.org/xen-devel/84486d84-4452-af18-f7e7-753faf5a125d@citrix.com/ So we believe this also affects Haswell, but the errata is not published for those CPUs (yet at least). If/when it's published I'm happy to add it, in the meantime I think we should go with what has been published by Intel. Roger.
On 22.05.2020 15:54, Roger Pau Monné wrote: > On Fri, May 22, 2020 at 03:42:10PM +0200, Jan Beulich wrote: >> On 21.05.2020 11:22, Roger Pau Monne wrote: >>> Apply a workaround for Intel errata BDX99, CLX30, SKX100, CFW125, >>> BDF104, BDH85, BDM135, KWB131: "A Pending Fixed Interrupt May Be >>> Dispatched Before an Interrupt of The Same Priority Completes". >> >> While the change looks good to me as far as Broadwell goes, I >> think it was before this posting that Andrew also pointed at >> a specific Haswell erratum instance, still on the v3 thread. >> Am I to imply a v5 will follow adding affected Haswell models >> to the table? > > Those refer to a different errata, see: > > https://lore.kernel.org/xen-devel/84486d84-4452-af18-f7e7-753faf5a125d@citrix.com/ > > So we believe this also affects Haswell, but the errata is not published > for those CPUs (yet at least). If/when it's published I'm happy to add > it, in the meantime I think we should go with what has been published > by Intel. Oh, sorry, yes - should have looked at the full thread again, not just Andrew's initial response. Reviewed-by: Jan Beulich <jbeulich@suse.com> Jan
diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c index 82f108d301..178cb607c2 100644 --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -548,7 +548,7 @@ void trace_exit_reason(u32 *irq_traced) } } -bool errata_c6_eoi_workaround(void) +bool errata_c6_workaround(void) { static int8_t __read_mostly fix_needed = -1; @@ -573,10 +573,40 @@ bool errata_c6_eoi_workaround(void) INTEL_FAM6_MODEL(0x2f), { } }; + /* + * Errata BDX99, CLX30, SKX100, CFW125, BDF104, BDH85, BDM135, KWB131: + * A Pending Fixed Interrupt May Be Dispatched Before an Interrupt of + * The Same Priority Completes. + * + * Resuming from C6 Sleep-State, with Fixed Interrupts of the same + * priority queued (in the corresponding bits of the IRR and ISR APIC + * registers), the processor may dispatch the second interrupt (from + * the IRR bit) before the first interrupt has completed and written to + * the EOI register, causing the first interrupt to never complete. + */ + static const struct x86_cpu_id isr_errata[] = { + /* Broadwell */ + INTEL_FAM6_MODEL(0x47), + INTEL_FAM6_MODEL(0x3d), + INTEL_FAM6_MODEL(0x4f), + INTEL_FAM6_MODEL(0x56), + /* Skylake (client) */ + INTEL_FAM6_MODEL(0x5e), + INTEL_FAM6_MODEL(0x4e), + /* {Sky/Cascade}lake (server) */ + INTEL_FAM6_MODEL(0x55), + /* {Kaby/Coffee/Whiskey/Amber} Lake */ + INTEL_FAM6_MODEL(0x9e), + INTEL_FAM6_MODEL(0x8e), + /* Cannon Lake */ + INTEL_FAM6_MODEL(0x66), + { } + }; #undef INTEL_FAM6_MODEL - fix_needed = cpu_has_apic && !directed_eoi_enabled && - x86_match_cpu(eoi_errata); + fix_needed = cpu_has_apic && + ((!directed_eoi_enabled && x86_match_cpu(eoi_errata)) || + x86_match_cpu(isr_errata)); } return (fix_needed && cpu_has_pending_apic_eoi()); @@ -685,7 +715,7 @@ static void acpi_processor_idle(void) return; } - if ( (cx->type >= ACPI_STATE_C3) && errata_c6_eoi_workaround() ) + if ( (cx->type >= ACPI_STATE_C3) && errata_c6_workaround() ) cx = power->safe_state; diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c index 88a3e160c5..52eab81bf8 100644 --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -770,7 +770,7 @@ static void mwait_idle(void) return; } - if ((cx->type >= 3) && errata_c6_eoi_workaround()) + if ((cx->type >= 3) && errata_c6_workaround()) cx = power->safe_state; eax = cx->address; diff --git a/xen/include/asm-x86/cpuidle.h b/xen/include/asm-x86/cpuidle.h index 51368694dc..0981a8fd64 100644 --- a/xen/include/asm-x86/cpuidle.h +++ b/xen/include/asm-x86/cpuidle.h @@ -26,6 +26,6 @@ void update_idle_stats(struct acpi_processor_power *, void update_last_cx_stat(struct acpi_processor_power *, struct acpi_processor_cx *, uint64_t); -bool errata_c6_eoi_workaround(void); +bool errata_c6_workaround(void); #endif /* __X86_ASM_CPUIDLE_H__ */
Apply a workaround for Intel errata BDX99, CLX30, SKX100, CFW125, BDF104, BDH85, BDM135, KWB131: "A Pending Fixed Interrupt May Be Dispatched Before an Interrupt of The Same Priority Completes". Apply the errata to all server and client models (big cores) from Broadwell to Cascade Lake. The workaround is grouped together with the existing fix for errata AAJ72, and the eoi from the function name is removed. Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> --- Changes since v3: - Remove command line option. - Switch order of static vs const. Changes since v2: - Use x86_match_cpu and apply the workaround to all models from Broadwell to Cascade Lake. - Rename command line option to disable-c6-errata. Changes since v1: - Unify workaround with errata_c6_eoi_workaround. - Properly check state in both acpi and mwait drivers. --- xen/arch/x86/acpi/cpu_idle.c | 38 +++++++++++++++++++++++++++++++---- xen/arch/x86/cpu/mwait-idle.c | 2 +- xen/include/asm-x86/cpuidle.h | 2 +- 3 files changed, 36 insertions(+), 6 deletions(-)