diff mbox series

[01/10] clk: qcom: clk-alpha-pll: remove unused/incorrect PLL_CAL_VAL

Message ID 20200524210615.17035-2-jonathan@marek.ca (mailing list archive)
State Changes Requested, archived
Headers show
Series Enable GPU for SM8150 and SM8250 | expand

Commit Message

Jonathan Marek May 24, 2020, 9:06 p.m. UTC
0x44 isn't a register offset, it is the value that goes into CAL_L_VAL.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
 drivers/clk/qcom/clk-alpha-pll.c | 2 --
 1 file changed, 2 deletions(-)

Comments

Stephen Boyd May 26, 2020, 11:21 p.m. UTC | #1
Quoting Jonathan Marek (2020-05-24 14:06:02)
> 0x44 isn't a register offset, it is the value that goes into CAL_L_VAL.
> 
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---

Any fixes tag?
Jonathan Marek May 26, 2020, 11:30 p.m. UTC | #2
On 5/26/20 7:21 PM, Stephen Boyd wrote:
> Quoting Jonathan Marek (2020-05-24 14:06:02)
>> 0x44 isn't a register offset, it is the value that goes into CAL_L_VAL.
>>
>> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
>> ---
> 
> Any fixes tag?
> 

This doesn't fix anything (its unused as the commit message says), does 
that still qualify for a fixes tag?
Stephen Boyd May 27, 2020, 2:42 a.m. UTC | #3
Quoting Jonathan Marek (2020-05-26 16:30:38)
> On 5/26/20 7:21 PM, Stephen Boyd wrote:
> > Quoting Jonathan Marek (2020-05-24 14:06:02)
> >> 0x44 isn't a register offset, it is the value that goes into CAL_L_VAL.
> >>
> >> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> >> ---
> > 
> > Any fixes tag?
> > 
> 
> This doesn't fix anything (its unused as the commit message says), does 
> that still qualify for a fixes tag?

Sure. Even if it's unused it could be used by someone who backported the
patch somewhere.
diff mbox series

Patch

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 9b2dfa08acb2..1325139173c9 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -56,7 +56,6 @@ 
 #define PLL_STATUS(p)		((p)->offset + (p)->regs[PLL_OFF_STATUS])
 #define PLL_OPMODE(p)		((p)->offset + (p)->regs[PLL_OFF_OPMODE])
 #define PLL_FRAC(p)		((p)->offset + (p)->regs[PLL_OFF_FRAC])
-#define PLL_CAL_VAL(p)		((p)->offset + (p)->regs[PLL_OFF_CAL_VAL])
 
 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
 	[CLK_ALPHA_PLL_TYPE_DEFAULT] =  {
@@ -115,7 +114,6 @@  const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
 		[PLL_OFF_STATUS] = 0x30,
 		[PLL_OFF_OPMODE] = 0x38,
 		[PLL_OFF_ALPHA_VAL] = 0x40,
-		[PLL_OFF_CAL_VAL] = 0x44,
 	},
 	[CLK_ALPHA_PLL_TYPE_LUCID] =  {
 		[PLL_OFF_L_VAL] = 0x04,