| Message ID | 1341443716-23509-1-git-send-email-eugeni.dodonov@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
2012/7/4 Eugeni Dodonov <eugeni.dodonov@intel.com>: > This is required for a stable FDI connection. > > v2: fix and simplify the FDI_RX_MISC bits as noticed by Paulo Zanoni. > > CC: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > drivers/gpu/drm/i915/intel_ddi.c | 9 +++++++++ > 2 files changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 5b0c5f6..287d277 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3849,6 +3849,9 @@ > #define _FDI_RXA_TUSIZE2 0xf0038 > #define _FDI_RXB_TUSIZE1 0xf1030 > #define _FDI_RXB_TUSIZE2 0xf1038 > +#define FDI_RX_TP1_TO_TP2_48 (2<<20) > +#define FDI_RX_TP1_TO_TP2_64 (3<<20) > +#define FDI_RX_FDI_DELAY_90 (0x90<<0) > #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) > #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) > #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index effb263..2d5acd2 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -170,6 +170,15 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) > > udelay(600); > > + /* We need to program FDI_RX_MISC with the default TP1 to TP2 > + * values before enabling the receiver, and configure the delay > + * for the FDI timing generator to 90h. Luckily, all the other > + * bits are supposed to be zeroed, so we can write those values > + * directly. > + */ > + I915_WRITE(FDI_RX_MISC(pipe), FDI_RX_TP1_TO_TP2_48 | > + FDI_RX_FDI_DELAY_90); > + > /* Enable CPU FDI Receiver with auto-training */ > reg = FDI_RX_CTL(pipe); > I915_WRITE(reg, > -- > 1.7.11.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Thu, Jul 05, 2012 at 09:58:53AM -0300, Paulo Zanoni wrote: > 2012/7/4 Eugeni Dodonov <eugeni.dodonov@intel.com>: > > This is required for a stable FDI connection. > > > > v2: fix and simplify the FDI_RX_MISC bits as noticed by Paulo Zanoni. > > > > CC: Paulo Zanoni <paulo.r.zanoni@intel.com> > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Patch queued for -next, thanks. -Daniel
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5b0c5f6..287d277 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3849,6 +3849,9 @@ #define _FDI_RXA_TUSIZE2 0xf0038 #define _FDI_RXB_TUSIZE1 0xf1030 #define _FDI_RXB_TUSIZE2 0xf1038 +#define FDI_RX_TP1_TO_TP2_48 (2<<20) +#define FDI_RX_TP1_TO_TP2_64 (3<<20) +#define FDI_RX_FDI_DELAY_90 (0x90<<0) #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index effb263..2d5acd2 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -170,6 +170,15 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) udelay(600); + /* We need to program FDI_RX_MISC with the default TP1 to TP2 + * values before enabling the receiver, and configure the delay + * for the FDI timing generator to 90h. Luckily, all the other + * bits are supposed to be zeroed, so we can write those values + * directly. + */ + I915_WRITE(FDI_RX_MISC(pipe), FDI_RX_TP1_TO_TP2_48 | + FDI_RX_FDI_DELAY_90); + /* Enable CPU FDI Receiver with auto-training */ reg = FDI_RX_CTL(pipe); I915_WRITE(reg,
This is required for a stable FDI connection. v2: fix and simplify the FDI_RX_MISC bits as noticed by Paulo Zanoni. CC: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_ddi.c | 9 +++++++++ 2 files changed, 12 insertions(+)