From patchwork Mon Jun 1 07:04:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 11581529 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D01F11667 for ; Mon, 1 Jun 2020 07:06:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AC515207FB for ; Mon, 1 Jun 2020 07:06:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="V3Um2iZK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728167AbgFAHGC (ORCPT ); Mon, 1 Jun 2020 03:06:02 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:49728 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727118AbgFAHGB (ORCPT ); Mon, 1 Jun 2020 03:06:01 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 05175QTg069541; Mon, 1 Jun 2020 02:05:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1590995126; bh=M6H6i0Eh/2aEE2Hihio/iMjOVmuBrf3WccAscdjEyLs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=V3Um2iZKeCIDPp82s7Hw7RTs/04nPa7j7mmYhd/IZRLx/OCD07nkxzIB9Dyjb93kk BFs3Wd+B0ky40j3DfxThgD7+ItxTmvZV7ppFJYfnXRsAopO2axDpymStgHIC1aPdvc 1zFDV+qYB9ZimkTMLhL8c9lI/QJDvhqOvAaID0lE= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 05175Qa0061997 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 1 Jun 2020 02:05:26 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 1 Jun 2020 02:05:26 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 1 Jun 2020 02:05:26 -0500 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 051758s5016257; Mon, 1 Jun 2020 02:05:20 -0500 From: Vignesh Raghavendra To: Tudor Ambarus , Mark Brown CC: Vignesh Raghavendra , Boris Brezillon , Ramuthevar Vadivel Murugan , , , , , , Subject: [RESEND PATCH v3 3/8] mtd: spi-nor: cadence-quadspi: Don't initialize rx_dma_complete on failure Date: Mon, 1 Jun 2020 12:34:39 +0530 Message-ID: <20200601070444.16923-4-vigneshr@ti.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200601070444.16923-1-vigneshr@ti.com> References: <20200601070444.16923-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org If driver fails to acquire DMA channel then don't initialize rx_dma_complete struct as it won't be used. Signed-off-by: Vignesh Raghavendra Reviewed-by: Tudor Ambarus --- drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi-nor/controllers/cadence-quadspi.c b/drivers/mtd/spi-nor/controllers/cadence-quadspi.c index 8a9e17f79d8d9..379e22c11c87f 100644 --- a/drivers/mtd/spi-nor/controllers/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/controllers/cadence-quadspi.c @@ -1180,6 +1180,7 @@ static void cqspi_request_mmap_dma(struct cqspi_st *cqspi) if (IS_ERR(cqspi->rx_chan)) { dev_err(&cqspi->pdev->dev, "No Rx DMA available\n"); cqspi->rx_chan = NULL; + return; } init_completion(&cqspi->rx_dma_complete); }