[v1,4/6] drm: panel-simple: add Hitachi 3.5" QVGA panel
diff mbox series

Message ID 20200601083309.712606-5-sam@ravnborg.org
State New
Headers show
Series
  • drm: add a few simple panels
Related show

Commit Message

Sam Ravnborg June 1, 2020, 8:33 a.m. UTC
This panel is used on evaluation boards for Atmel at91sam9261 and
at91sam6263.

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
---
 drivers/gpu/drm/panel/panel-simple.c | 29 ++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

Comments

Douglas Anderson June 2, 2020, 12:30 a.m. UTC | #1
Hi,

On Mon, Jun 1, 2020 at 1:33 AM Sam Ravnborg <sam@ravnborg.org> wrote:
>
> This panel is used on evaluation boards for Atmel at91sam9261 and
> at91sam6263.
>
> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
> Cc: Thierry Reding <thierry.reding@gmail.com>
> Cc: Sam Ravnborg <sam@ravnborg.org>
> ---
>  drivers/gpu/drm/panel/panel-simple.c | 29 ++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
>
> diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> index 8624bb80108c..25c96639631f 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -1813,6 +1813,32 @@ static const struct panel_desc hannstar_hsd100pxn1 = {
>         .connector_type = DRM_MODE_CONNECTOR_LVDS,
>  };
>
> +static const struct drm_display_mode hitachi_tx09d71vm1cca_mode = {
> +       .clock = 4965000,

This is the pixel clock in kHz, right?  So it runs at almost 5 Terahertz?


> +       .hdisplay = 240,
> +       .hsync_start = 240 + 0,
> +       .hsync_end = 240 + 0 + 5,
> +       .htotal = 240 + 0 + 5 + 1,
> +       .vdisplay = 320,
> +       .vsync_start = 320 + 0,
> +       .vsync_end = 320 + 0 + 1,
> +       .vtotal = 320 + 0 + 1 + 1,

Some random datasheet I found has really different numbers.  If the
numbers above are what everyone is using then I suppose it's fine,
just curious why the mismatch.

Also: should you provide "vrefresh"?



-Doug
Sam Ravnborg June 5, 2020, 5:19 p.m. UTC | #2
Hi Doug.

On Mon, Jun 01, 2020 at 05:30:53PM -0700, Doug Anderson wrote:
> Hi,
> 
> On Mon, Jun 1, 2020 at 1:33 AM Sam Ravnborg <sam@ravnborg.org> wrote:
> >
> > This panel is used on evaluation boards for Atmel at91sam9261 and
> > at91sam6263.
> >
> > Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
> > Cc: Thierry Reding <thierry.reding@gmail.com>
> > Cc: Sam Ravnborg <sam@ravnborg.org>
> > ---
> >  drivers/gpu/drm/panel/panel-simple.c | 29 ++++++++++++++++++++++++++++
> >  1 file changed, 29 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> > index 8624bb80108c..25c96639631f 100644
> > --- a/drivers/gpu/drm/panel/panel-simple.c
> > +++ b/drivers/gpu/drm/panel/panel-simple.c
> > @@ -1813,6 +1813,32 @@ static const struct panel_desc hannstar_hsd100pxn1 = {
> >         .connector_type = DRM_MODE_CONNECTOR_LVDS,
> >  };
> >
> > +static const struct drm_display_mode hitachi_tx09d71vm1cca_mode = {
> > +       .clock = 4965000,
> 
> This is the pixel clock in kHz, right?  So it runs at almost 5 Terahertz?
> 
> 
> > +       .hdisplay = 240,
> > +       .hsync_start = 240 + 0,
> > +       .hsync_end = 240 + 0 + 5,
> > +       .htotal = 240 + 0 + 5 + 1,
> > +       .vdisplay = 320,
> > +       .vsync_start = 320 + 0,
> > +       .vsync_end = 320 + 0 + 1,
> > +       .vtotal = 320 + 0 + 1 + 1,
> 
> Some random datasheet I found has really different numbers.  If the
> numbers above are what everyone is using then I suppose it's fine,
> just curious why the mismatch.

The timing comes from:
arch/arm/boot/dts/at91sam9263ek.dts - that include display timings for
the panel on the evaluation board.
I did not verify any datasheet - I just blindly copied what was there.
And clock was obviously not properly adjusted to khz.

Will fix in v2 - will also try to find a datasheet this time.

Thanks for noticing!

	Sam

Patch
diff mbox series

diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index 8624bb80108c..25c96639631f 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -1813,6 +1813,32 @@  static const struct panel_desc hannstar_hsd100pxn1 = {
 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
 };
 
+static const struct drm_display_mode hitachi_tx09d71vm1cca_mode = {
+	.clock = 4965000,
+	.hdisplay = 240,
+	.hsync_start = 240 + 0,
+	.hsync_end = 240 + 0 + 5,
+	.htotal = 240 + 0 + 5 + 1,
+	.vdisplay = 320,
+	.vsync_start = 320 + 0,
+	.vsync_end = 320 + 0 + 1,
+	.vtotal = 320 + 0 + 1 + 1,
+	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
+};
+
+static const struct panel_desc hitachi_tx09d71vm1cca = {
+	.modes = &hitachi_tx09d71vm1cca_mode,
+	.num_modes = 1,
+	.bpc = 6,
+	.size = {
+		.width = 54,
+		.height = 72,
+	},
+	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
+	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
+	.connector_type = DRM_MODE_CONNECTOR_DPI,
+};
+
 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
 	.clock = 33333,
 	.hdisplay = 800,
@@ -3737,6 +3763,9 @@  static const struct of_device_id platform_of_match[] = {
 	}, {
 		.compatible = "hannstar,hsd100pxn1",
 		.data = &hannstar_hsd100pxn1,
+	}, {
+		.compatible = "hit,tx09d71vm1cca",
+		.data = &hitachi_tx09d71vm1cca,
 	}, {
 		.compatible = "hit,tx23d38vm0caa",
 		.data = &hitachi_tx23d38vm0caa