[v6,5/5] cpufreq: qcom: Disable fast switch when scaling DDR/L3
diff mbox series

Message ID 20200605213332.609-6-sibis@codeaurora.org
State New
Delegated to: viresh kumar
Headers show
Series
  • DDR/L3 Scaling support on SDM845 and SC7180 SoCs
Related show

Commit Message

Sibi Sankar June 5, 2020, 9:33 p.m. UTC
Disable fast switch when the opp-tables required for scaling DDR/L3
are populated.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---

v6:
 * No change

v5:
 * Drop dev_pm_opp_get_path_count [Saravana]

 drivers/cpufreq/qcom-cpufreq-hw.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Matthias Kaehlcke June 15, 2020, 5:32 p.m. UTC | #1
On Sat, Jun 06, 2020 at 03:03:32AM +0530, Sibi Sankar wrote:
> Disable fast switch when the opp-tables required for scaling DDR/L3
> are populated.
> 
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>

not sure a separate patch is needed for this, but anyway:

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>

Patch
diff mbox series

diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c
index 8fa6ab6e0e4b6..56f01049fd3a3 100644
--- a/drivers/cpufreq/qcom-cpufreq-hw.c
+++ b/drivers/cpufreq/qcom-cpufreq-hw.c
@@ -158,6 +158,8 @@  static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
 	} else if (ret != -ENODEV) {
 		dev_err(cpu_dev, "Invalid opp table in device tree\n");
 		return ret;
+	} else {
+		policy->fast_switch_possible = true;
 	}
 
 	for (i = 0; i < LUT_MAX_ENTRIES; i++) {
@@ -307,8 +309,6 @@  static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
 
 	dev_pm_opp_of_register_em(policy->cpus);
 
-	policy->fast_switch_possible = true;
-
 	return 0;
 error:
 	devm_iounmap(dev, base);