Message ID | 1591603981-16879-3-git-send-email-pmorel@linux.ibm.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | s390x: Testing the Channel Subsystem I/O | expand |
On 08/06/2020 10.12, Pierre Morel wrote: > While adding the definition for the AFP-Register control bit, move all > existing definitions for CR0 out of the C zone to the assmbler zone to > keep the definitions concerning CR0 together. > > Signed-off-by: Pierre Morel <pmorel@linux.ibm.com> > Reviewed-by: David Hildenbrand <david@redhat.com> > Reviewed-by: Janosch Frank <frankja@linux.ibm.com> > Reviewed-by: Cornelia Huck <cohuck@redhat.com> > --- > lib/s390x/asm/arch_def.h | 11 ++++++----- > s390x/cstart64.S | 2 +- > 2 files changed, 7 insertions(+), 6 deletions(-) > > diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h > index 5388114..12045ff 100644 > --- a/lib/s390x/asm/arch_def.h > +++ b/lib/s390x/asm/arch_def.h > @@ -19,17 +19,18 @@ > > #define PSW_EXCEPTION_MASK (PSW_MASK_EA | PSW_MASK_BA) > > +#define CR0_EXTM_SCLP 0x0000000000000200UL > +#define CR0_EXTM_EXTC 0x0000000000002000UL > +#define CR0_EXTM_EMGC 0x0000000000004000UL > +#define CR0_EXTM_MASK 0x0000000000006200UL > +#define CR0_AFP_REG_CRTL 0x0000000000040000UL > + > #ifndef __ASSEMBLER__ > struct psw { > uint64_t mask; > uint64_t addr; > }; > > -#define CR0_EXTM_SCLP 0x0000000000000200UL > -#define CR0_EXTM_EXTC 0x0000000000002000UL > -#define CR0_EXTM_EMGC 0x0000000000004000UL > -#define CR0_EXTM_MASK 0x0000000000006200UL > - > struct lowcore { > uint8_t pad_0x0000[0x0080 - 0x0000]; /* 0x0000 */ > uint32_t ext_int_param; /* 0x0080 */ > diff --git a/s390x/cstart64.S b/s390x/cstart64.S > index 6e85635..b50c42c 100644 > --- a/s390x/cstart64.S > +++ b/s390x/cstart64.S > @@ -214,4 +214,4 @@ svc_int_psw: > .quad PSW_EXCEPTION_MASK, svc_int > initial_cr0: > /* enable AFP-register control, so FP regs (+BFP instr) can be used */ > - .quad 0x0000000000040000 > + .quad CR0_AFP_REG_CRTL > Acked-by: Thomas Huth <thuth@redhat.com>
On 2020-06-08 10:45, Thomas Huth wrote: > On 08/06/2020 10.12, Pierre Morel wrote: >> While adding the definition for the AFP-Register control bit, move all >> existing definitions for CR0 out of the C zone to the assmbler zone to >> keep the definitions concerning CR0 together. >> >> Signed-off-by: Pierre Morel <pmorel@linux.ibm.com> >> Reviewed-by: David Hildenbrand <david@redhat.com> >> Reviewed-by: Janosch Frank <frankja@linux.ibm.com> >> Reviewed-by: Cornelia Huck <cohuck@redhat.com> >> --- >> lib/s390x/asm/arch_def.h | 11 ++++++----- >> s390x/cstart64.S | 2 +- >> 2 files changed, 7 insertions(+), 6 deletions(-) >> >> diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h >> index 5388114..12045ff 100644 >> --- a/lib/s390x/asm/arch_def.h >> +++ b/lib/s390x/asm/arch_def.h >> @@ -19,17 +19,18 @@ >> >> #define PSW_EXCEPTION_MASK (PSW_MASK_EA | PSW_MASK_BA) >> >> +#define CR0_EXTM_SCLP 0x0000000000000200UL >> +#define CR0_EXTM_EXTC 0x0000000000002000UL >> +#define CR0_EXTM_EMGC 0x0000000000004000UL >> +#define CR0_EXTM_MASK 0x0000000000006200UL >> +#define CR0_AFP_REG_CRTL 0x0000000000040000UL >> + >> #ifndef __ASSEMBLER__ >> struct psw { >> uint64_t mask; >> uint64_t addr; >> }; >> >> -#define CR0_EXTM_SCLP 0x0000000000000200UL >> -#define CR0_EXTM_EXTC 0x0000000000002000UL >> -#define CR0_EXTM_EMGC 0x0000000000004000UL >> -#define CR0_EXTM_MASK 0x0000000000006200UL >> - >> struct lowcore { >> uint8_t pad_0x0000[0x0080 - 0x0000]; /* 0x0000 */ >> uint32_t ext_int_param; /* 0x0080 */ >> diff --git a/s390x/cstart64.S b/s390x/cstart64.S >> index 6e85635..b50c42c 100644 >> --- a/s390x/cstart64.S >> +++ b/s390x/cstart64.S >> @@ -214,4 +214,4 @@ svc_int_psw: >> .quad PSW_EXCEPTION_MASK, svc_int >> initial_cr0: >> /* enable AFP-register control, so FP regs (+BFP instr) can be used */ >> - .quad 0x0000000000040000 >> + .quad CR0_AFP_REG_CRTL >> > > Acked-by: Thomas Huth <thuth@redhat.com> > Thanks, Pierre
diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h index 5388114..12045ff 100644 --- a/lib/s390x/asm/arch_def.h +++ b/lib/s390x/asm/arch_def.h @@ -19,17 +19,18 @@ #define PSW_EXCEPTION_MASK (PSW_MASK_EA | PSW_MASK_BA) +#define CR0_EXTM_SCLP 0x0000000000000200UL +#define CR0_EXTM_EXTC 0x0000000000002000UL +#define CR0_EXTM_EMGC 0x0000000000004000UL +#define CR0_EXTM_MASK 0x0000000000006200UL +#define CR0_AFP_REG_CRTL 0x0000000000040000UL + #ifndef __ASSEMBLER__ struct psw { uint64_t mask; uint64_t addr; }; -#define CR0_EXTM_SCLP 0x0000000000000200UL -#define CR0_EXTM_EXTC 0x0000000000002000UL -#define CR0_EXTM_EMGC 0x0000000000004000UL -#define CR0_EXTM_MASK 0x0000000000006200UL - struct lowcore { uint8_t pad_0x0000[0x0080 - 0x0000]; /* 0x0000 */ uint32_t ext_int_param; /* 0x0080 */ diff --git a/s390x/cstart64.S b/s390x/cstart64.S index 6e85635..b50c42c 100644 --- a/s390x/cstart64.S +++ b/s390x/cstart64.S @@ -214,4 +214,4 @@ svc_int_psw: .quad PSW_EXCEPTION_MASK, svc_int initial_cr0: /* enable AFP-register control, so FP regs (+BFP instr) can be used */ - .quad 0x0000000000040000 + .quad CR0_AFP_REG_CRTL