| Message ID | 1591625864-31494-8-git-send-email-bmeng.cn@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support | expand |
On Mon, Jun 8, 2020 at 7:24 AM Bin Meng <bmeng.cn@gmail.com> wrote: > > From: Bin Meng <bin.meng@windriver.com> > > SiFive FU540 SoC integrates a GPIO controller with 16 GPIO lines. > This hooks the exsiting SiFive GPIO model to the SoC, and adds its > device tree data as well. > > Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > > hw/riscv/sifive_u.c | 44 ++++++++++++++++++++++++++++++++++++++++++-- > include/hw/riscv/sifive_u.h | 19 +++++++++++++++++++ > 2 files changed, 61 insertions(+), 2 deletions(-) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 8dc6842..881949b 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -11,8 +11,9 @@ > * 1) CLINT (Core Level Interruptor) > * 2) PLIC (Platform Level Interrupt Controller) > * 3) PRCI (Power, Reset, Clock, Interrupt) > - * 4) OTP (One-Time Programmable) memory with stored serial number > - * 5) GEM (Gigabit Ethernet Controller) and management block > + * 4) GPIO (General Purpose Input/Output Controller) > + * 5) OTP (One-Time Programmable) memory with stored serial number > + * 6) GEM (Gigabit Ethernet Controller) and management block > * > * This board currently generates devicetree dynamically that indicates at least > * two harts and up to five harts. > @@ -75,6 +76,7 @@ static const struct MemmapEntry { > [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 }, > [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, > [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, > + [SIFIVE_U_GPIO] = { 0x10060000, 0x1000 }, > [SIFIVE_U_OTP] = { 0x10070000, 0x1000 }, > [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 }, > [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, > @@ -268,6 +270,28 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, > g_free(cells); > g_free(nodename); > > + nodename = g_strdup_printf("/soc/gpio@%lx", > + (long)memmap[SIFIVE_U_GPIO].base); > + qemu_fdt_add_subnode(fdt, nodename); > + qemu_fdt_setprop_cells(fdt, nodename, "clocks", > + prci_phandle, PRCI_CLK_TLCLK); > + qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2); > + qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); > + qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2); > + qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); > + qemu_fdt_setprop_cells(fdt, nodename, "reg", > + 0x0, memmap[SIFIVE_U_GPIO].base, > + 0x0, memmap[SIFIVE_U_GPIO].size); > + qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0, > + SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3, > + SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6, > + SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9, > + SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12, > + SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15); > + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); > + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0"); > + g_free(nodename); > + > phy_phandle = phandle++; > nodename = g_strdup_printf("/soc/ethernet@%lx", > (long)memmap[SIFIVE_U_GEM].base); > @@ -525,6 +549,8 @@ static void sifive_u_soc_instance_init(Object *obj) > > sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci), > TYPE_SIFIVE_U_PRCI); > + sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio), > + TYPE_SIFIVE_GPIO); > sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp), > TYPE_SIFIVE_U_OTP); > sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem), > @@ -618,6 +644,20 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) > object_property_set_bool(OBJECT(&s->prci), true, "realized", &err); > sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base); > > + qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16); > + object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_GPIO].base); > + > + /* Pass all GPIOs to the SOC layer so they are available to the board */ > + qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); > + > + /* Connect GPIO interrupts to the PLIC */ > + for (i = 0; i < 16; i++) { > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, > + qdev_get_gpio_in(DEVICE(s->plic), > + SIFIVE_U_GPIO_IRQ0 + i)); > + } > + > qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); > object_property_set_bool(OBJECT(&s->otp), true, "realized", &err); > sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base); > diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h > index 16c297e..dcf7f3b 100644 > --- a/include/hw/riscv/sifive_u.h > +++ b/include/hw/riscv/sifive_u.h > @@ -22,6 +22,7 @@ > #include "hw/net/cadence_gem.h" > #include "hw/riscv/riscv_hart.h" > #include "hw/riscv/sifive_cpu.h" > +#include "hw/riscv/sifive_gpio.h" > #include "hw/riscv/sifive_u_prci.h" > #include "hw/riscv/sifive_u_otp.h" > > @@ -40,6 +41,7 @@ typedef struct SiFiveUSoCState { > RISCVHartArrayState u_cpus; > DeviceState *plic; > SiFiveUPRCIState prci; > + SIFIVEGPIOState gpio; > SiFiveUOTPState otp; > CadenceGEMState gem; > > @@ -73,6 +75,7 @@ enum { > SIFIVE_U_PRCI, > SIFIVE_U_UART0, > SIFIVE_U_UART1, > + SIFIVE_U_GPIO, > SIFIVE_U_OTP, > SIFIVE_U_FLASH0, > SIFIVE_U_DRAM, > @@ -83,6 +86,22 @@ enum { > enum { > SIFIVE_U_UART0_IRQ = 4, > SIFIVE_U_UART1_IRQ = 5, > + SIFIVE_U_GPIO_IRQ0 = 7, > + SIFIVE_U_GPIO_IRQ1 = 8, > + SIFIVE_U_GPIO_IRQ2 = 9, > + SIFIVE_U_GPIO_IRQ3 = 10, > + SIFIVE_U_GPIO_IRQ4 = 11, > + SIFIVE_U_GPIO_IRQ5 = 12, > + SIFIVE_U_GPIO_IRQ6 = 13, > + SIFIVE_U_GPIO_IRQ7 = 14, > + SIFIVE_U_GPIO_IRQ8 = 15, > + SIFIVE_U_GPIO_IRQ9 = 16, > + SIFIVE_U_GPIO_IRQ10 = 17, > + SIFIVE_U_GPIO_IRQ11 = 18, > + SIFIVE_U_GPIO_IRQ12 = 19, > + SIFIVE_U_GPIO_IRQ13 = 20, > + SIFIVE_U_GPIO_IRQ14 = 21, > + SIFIVE_U_GPIO_IRQ15 = 22, > SIFIVE_U_GEM_IRQ = 0x35 > }; > > -- > 2.7.4 > >
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 8dc6842..881949b 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -11,8 +11,9 @@ * 1) CLINT (Core Level Interruptor) * 2) PLIC (Platform Level Interrupt Controller) * 3) PRCI (Power, Reset, Clock, Interrupt) - * 4) OTP (One-Time Programmable) memory with stored serial number - * 5) GEM (Gigabit Ethernet Controller) and management block + * 4) GPIO (General Purpose Input/Output Controller) + * 5) OTP (One-Time Programmable) memory with stored serial number + * 6) GEM (Gigabit Ethernet Controller) and management block * * This board currently generates devicetree dynamically that indicates at least * two harts and up to five harts. @@ -75,6 +76,7 @@ static const struct MemmapEntry { [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 }, [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, + [SIFIVE_U_GPIO] = { 0x10060000, 0x1000 }, [SIFIVE_U_OTP] = { 0x10070000, 0x1000 }, [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 }, [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, @@ -268,6 +270,28 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, g_free(cells); g_free(nodename); + nodename = g_strdup_printf("/soc/gpio@%lx", + (long)memmap[SIFIVE_U_GPIO].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cells(fdt, nodename, "clocks", + prci_phandle, PRCI_CLK_TLCLK); + qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2); + qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2); + qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U_GPIO].base, + 0x0, memmap[SIFIVE_U_GPIO].size); + qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0, + SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3, + SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6, + SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9, + SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12, + SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0"); + g_free(nodename); + phy_phandle = phandle++; nodename = g_strdup_printf("/soc/ethernet@%lx", (long)memmap[SIFIVE_U_GEM].base); @@ -525,6 +549,8 @@ static void sifive_u_soc_instance_init(Object *obj) sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci), TYPE_SIFIVE_U_PRCI); + sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio), + TYPE_SIFIVE_GPIO); sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp), TYPE_SIFIVE_U_OTP); sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem), @@ -618,6 +644,20 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) object_property_set_bool(OBJECT(&s->prci), true, "realized", &err); sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base); + qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16); + object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_GPIO].base); + + /* Pass all GPIOs to the SOC layer so they are available to the board */ + qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); + + /* Connect GPIO interrupts to the PLIC */ + for (i = 0; i < 16; i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, + qdev_get_gpio_in(DEVICE(s->plic), + SIFIVE_U_GPIO_IRQ0 + i)); + } + qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); object_property_set_bool(OBJECT(&s->otp), true, "realized", &err); sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 16c297e..dcf7f3b 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -22,6 +22,7 @@ #include "hw/net/cadence_gem.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_cpu.h" +#include "hw/riscv/sifive_gpio.h" #include "hw/riscv/sifive_u_prci.h" #include "hw/riscv/sifive_u_otp.h" @@ -40,6 +41,7 @@ typedef struct SiFiveUSoCState { RISCVHartArrayState u_cpus; DeviceState *plic; SiFiveUPRCIState prci; + SIFIVEGPIOState gpio; SiFiveUOTPState otp; CadenceGEMState gem; @@ -73,6 +75,7 @@ enum { SIFIVE_U_PRCI, SIFIVE_U_UART0, SIFIVE_U_UART1, + SIFIVE_U_GPIO, SIFIVE_U_OTP, SIFIVE_U_FLASH0, SIFIVE_U_DRAM, @@ -83,6 +86,22 @@ enum { enum { SIFIVE_U_UART0_IRQ = 4, SIFIVE_U_UART1_IRQ = 5, + SIFIVE_U_GPIO_IRQ0 = 7, + SIFIVE_U_GPIO_IRQ1 = 8, + SIFIVE_U_GPIO_IRQ2 = 9, + SIFIVE_U_GPIO_IRQ3 = 10, + SIFIVE_U_GPIO_IRQ4 = 11, + SIFIVE_U_GPIO_IRQ5 = 12, + SIFIVE_U_GPIO_IRQ6 = 13, + SIFIVE_U_GPIO_IRQ7 = 14, + SIFIVE_U_GPIO_IRQ8 = 15, + SIFIVE_U_GPIO_IRQ9 = 16, + SIFIVE_U_GPIO_IRQ10 = 17, + SIFIVE_U_GPIO_IRQ11 = 18, + SIFIVE_U_GPIO_IRQ12 = 19, + SIFIVE_U_GPIO_IRQ13 = 20, + SIFIVE_U_GPIO_IRQ14 = 21, + SIFIVE_U_GPIO_IRQ15 = 22, SIFIVE_U_GEM_IRQ = 0x35 };