| Message ID | 20200611174838.2822533-1-srinivas.pandruvada@linux.intel.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | cpufreq: intel_pstate: Add additional OOB enabling bit | expand |
On 2020.06.11 10:49 Srinivas Pandruvada wrote: > Add additional bit for OOB (Out of band) enabling of P-states. In this > case intel_pstate shouldn't load. Currently, only "BIT(8) == 1" of the > MSR MSR_MISC_PWR_MGMT is considered as OOB. Also add "BIT(18) == 1" as > OOB condition. Shouldn't those bits be defined in these files: arch/x86/include/asm/msr-index.h and tools/arch/x86/include/asm/msr-index.h ? By the way, I couldn't find those bits defined in Intel docs that I have. > > Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> > --- > drivers/cpufreq/intel_pstate.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c > index 8e23a698ce04..f21761443c90 100644 > --- a/drivers/cpufreq/intel_pstate.c > +++ b/drivers/cpufreq/intel_pstate.c > @@ -2686,8 +2686,8 @@ static bool __init intel_pstate_platform_pwr_mgmt_exists(void) > id = x86_match_cpu(intel_pstate_cpu_oob_ids); > if (id) { > rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); > - if (misc_pwr & (1 << 8)) { > - pr_debug("Bit 8 in the MISC_PWR_MGMT MSR set\n"); > + if ((misc_pwr & BIT(8)) || (misc_pwr & BIT(18))) { And then those bit definitions used above. > + pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n"); And then some insight also printed with the debug message. At least say "Out of Band". > return true; > } > } > -- > 2.24.1
On Fri, 2020-06-12 at 07:11 -0700, Doug Smythies wrote: > On 2020.06.11 10:49 Srinivas Pandruvada wrote: > > > Add additional bit for OOB (Out of band) enabling of P-states. In > > this > > case intel_pstate shouldn't load. Currently, only "BIT(8) == 1" of > > the > > MSR MSR_MISC_PWR_MGMT is considered as OOB. Also add "BIT(18) == 1" > > as > > OOB condition. > > Shouldn't those bits be defined in these files: > arch/x86/include/asm/msr-index.h > and > tools/arch/x86/include/asm/msr-index.h > > ? The rule from arch-x86 maintainers requires use in more than one place to go there. > > By the way, I couldn't find those bits defined in Intel docs that I > have. Usually, they end up in data sheets. > > > Signed-off-by: Srinivas Pandruvada < > > srinivas.pandruvada@linux.intel.com> > > --- > > drivers/cpufreq/intel_pstate.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/cpufreq/intel_pstate.c > > b/drivers/cpufreq/intel_pstate.c > > index 8e23a698ce04..f21761443c90 100644 > > --- a/drivers/cpufreq/intel_pstate.c > > +++ b/drivers/cpufreq/intel_pstate.c > > @@ -2686,8 +2686,8 @@ static bool __init > > intel_pstate_platform_pwr_mgmt_exists(void) > > id = x86_match_cpu(intel_pstate_cpu_oob_ids); > > if (id) { > > rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); > > - if (misc_pwr & (1 << 8)) { > > - pr_debug("Bit 8 in the MISC_PWR_MGMT MSR > > set\n"); > > + if ((misc_pwr & BIT(8)) || (misc_pwr & BIT(18))) { > > And then those bit definitions used above. I didn't understand the comment. > > > + pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR > > set\n"); > > And then some insight also printed with the debug message. > At least say "Out of Band". We can. Thanks, Srinivas > > > return true; > > } > > } > > -- > > 2.24.1 > >
diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c index 8e23a698ce04..f21761443c90 100644 --- a/drivers/cpufreq/intel_pstate.c +++ b/drivers/cpufreq/intel_pstate.c @@ -2686,8 +2686,8 @@ static bool __init intel_pstate_platform_pwr_mgmt_exists(void) id = x86_match_cpu(intel_pstate_cpu_oob_ids); if (id) { rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); - if (misc_pwr & (1 << 8)) { - pr_debug("Bit 8 in the MISC_PWR_MGMT MSR set\n"); + if ((misc_pwr & BIT(8)) || (misc_pwr & BIT(18))) { + pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n"); return true; } }
Add additional bit for OOB (Out of band) enabling of P-states. In this case intel_pstate shouldn't load. Currently, only "BIT(8) == 1" of the MSR MSR_MISC_PWR_MGMT is considered as OOB. Also add "BIT(18) == 1" as OOB condition. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> --- drivers/cpufreq/intel_pstate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)