| Message ID | 20200618184041.GE27951@zn.tnic (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | EDAC/amd64: Read back the scrub rate PCI register on F15h | expand |
On Thu, Jun 18, 2020 at 08:40:41PM +0200, Borislav Petkov wrote: > On Thu, Jun 18, 2020 at 07:56:46PM +0200, Borislav Petkov wrote: > > Oh, you're manipulating it alright but there's a bug in reporting it. > > Wanna test a patch? > > Here it is: > > --- > From: Borislav Petkov <bp@suse.de> > > Commit: > > da92110dfdfa ("EDAC, amd64_edac: Extend scrub rate support to F15hM60h") > > added support for F15h, model 0x60 CPUs but in doing so, missed to read > back SCRCTRL PCI config register on F15h CPUs which are *not* model > 0x60. Add that read so that doing > > $ cat /sys/devices/system/edac/mc/mc0/sdram_scrub_rate > > can show the previously set DRAM scrub rate. > > Fixes: da92110dfdfa ("EDAC, amd64_edac: Extend scrub rate support to F15hM60h") > Reported-by: Anders Andersson <pipatron@gmail.com> > Signed-off-by: Borislav Petkov <bp@suse.de> > Cc: <stable@vger.kernel.org> #v4.4.. > Link: https://lkml.kernel.org/r/CAKkunMbNWppx_i6xSdDHLseA2QQmGJqj_crY=NF-GZML5np4Vw@mail.gmail.com > --- > drivers/edac/amd64_edac.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c > index ef90070a9194..6262f6370c5d 100644 > --- a/drivers/edac/amd64_edac.c > +++ b/drivers/edac/amd64_edac.c > @@ -269,6 +269,8 @@ static int get_scrub_rate(struct mem_ctl_info *mci) > > if (pvt->model == 0x60) > amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval); > + else > + amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); > } else { > amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); > } > -- Queued into edac-urgent. Thx.
On Mon, Jun 22, 2020 at 5:13 PM Borislav Petkov <bp@alien8.de> wrote: > > On Thu, Jun 18, 2020 at 08:40:41PM +0200, Borislav Petkov wrote: > > On Thu, Jun 18, 2020 at 07:56:46PM +0200, Borislav Petkov wrote: > > > Oh, you're manipulating it alright but there's a bug in reporting it. > > > Wanna test a patch? > > > > Here it is: > > > > --- > > From: Borislav Petkov <bp@suse.de> > > > > Commit: > > > > da92110dfdfa ("EDAC, amd64_edac: Extend scrub rate support to F15hM60h") > > > > added support for F15h, model 0x60 CPUs but in doing so, missed to read > > back SCRCTRL PCI config register on F15h CPUs which are *not* model > > 0x60. Add that read so that doing > > > > $ cat /sys/devices/system/edac/mc/mc0/sdram_scrub_rate > > > > can show the previously set DRAM scrub rate. > > > > Fixes: da92110dfdfa ("EDAC, amd64_edac: Extend scrub rate support to F15hM60h") > > Reported-by: Anders Andersson <pipatron@gmail.com> > > Signed-off-by: Borislav Petkov <bp@suse.de> > > Cc: <stable@vger.kernel.org> #v4.4.. > > Link: https://lkml.kernel.org/r/CAKkunMbNWppx_i6xSdDHLseA2QQmGJqj_crY=NF-GZML5np4Vw@mail.gmail.com > > --- > > drivers/edac/amd64_edac.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c > > index ef90070a9194..6262f6370c5d 100644 > > --- a/drivers/edac/amd64_edac.c > > +++ b/drivers/edac/amd64_edac.c > > @@ -269,6 +269,8 @@ static int get_scrub_rate(struct mem_ctl_info *mci) > > > > if (pvt->model == 0x60) > > amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval); > > + else > > + amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); > > } else { > > amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); > > } > > -- > > Queued into edac-urgent. > > Thx. > > -- > Regards/Gruss, > Boris. > > https://people.kernel.org/tglx/notes-about-netiquette Ok, finally tested the patch on my machine, and (no surprise) everything now works as expected, thanks! // Anders
On Tue, Jun 23, 2020 at 03:41:35AM +0200, Anders Andersson wrote: > Ok, finally tested the patch on my machine, and (no surprise) > everything now works as expected, thanks! Thanks for testing, patch will appear upstream and in stable soon.
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index ef90070a9194..6262f6370c5d 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -269,6 +269,8 @@ static int get_scrub_rate(struct mem_ctl_info *mci) if (pvt->model == 0x60) amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval); + else + amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); } else { amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); }