| Message ID | 20200620160136.21584-1-martin.blumenstingl@googlemail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: dts: amlogic: Add the Ethernet "timing-adjustment" clock | expand |
On Sat, Jun 20, 2020 at 06:01:36PM +0200, Martin Blumenstingl wrote: > Add the "timing-adjusment" clock now that we now that this is connected > to the PRG_ETHERNET registers. It is used internally to generate the > RGMII RX delay no the MAC side (if needed). s/no/on Sort of typ0 i make :-) Andrew
Hi Andrew, On Sat, Jun 20, 2020 at 6:14 PM Andrew Lunn <andrew@lunn.ch> wrote: > > On Sat, Jun 20, 2020 at 06:01:36PM +0200, Martin Blumenstingl wrote: > > Add the "timing-adjusment" clock now that we now that this is connected > > to the PRG_ETHERNET registers. It is used internally to generate the > > RGMII RX delay no the MAC side (if needed). > > s/no/on > > Sort of typ0 i make :-) good catch, thanks! while going through this I also noticed that there's a typ0 in "timing-adjustment" (in the commit message only) and the word "know". I'll fix all of this and re-send Martin
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 8e6281c685fa..b9efc8469265 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -181,8 +181,10 @@ ethmac: ethernet@ff3f0000 { interrupt-names = "macirq"; clocks = <&clkc CLKID_ETH>, <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; + <&clkc CLKID_MPLL2>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "stmmaceth", "clkin0", "clkin1", + "timing-adjustment"; rx-fifo-depth = <4096>; tx-fifo-depth = <2048>; status = "disabled"; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index 593a006f4b7b..41805f2ed8fc 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -185,8 +185,10 @@ ethmac: ethernet@ff3f0000 { interrupt-names = "macirq"; clocks = <&clkc CLKID_ETH>, <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; + <&clkc CLKID_MPLL2>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "stmmaceth", "clkin0", "clkin1", + "timing-adjustment"; rx-fifo-depth = <4096>; tx-fifo-depth = <2048>; status = "disabled"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 234490d3ee68..03c25b9facff 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -333,8 +333,9 @@ &efuse { ðmac { clocks = <&clkc CLKID_ETH>, <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; + <&clkc CLKID_MPLL2>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; }; &gpio_intc { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index fc59c8534c0f..60484bbc7272 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -131,8 +131,9 @@ &efuse { ðmac { clocks = <&clkc CLKID_ETH>, <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; + <&clkc CLKID_MPLL2>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; mdio0: mdio { #address-cells = <1>;
Add the "timing-adjusment" clock now that we now that this is connected to the PRG_ETHERNET registers. It is used internally to generate the RGMII RX delay no the MAC side (if needed). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 6 ++++-- arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 6 ++++-- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 5 +++-- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 5 +++-- 4 files changed, 14 insertions(+), 8 deletions(-)