| Message ID | 20200623045957.1649059-2-ayaz.siddiqui@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/gt: Initialize reserved and unspecified MOCS indices | expand |
On Tue, Jun 23, 2020 at 10:29:57AM +0530, Ayaz A Siddiqui wrote: >In order to avoid functional breakage of mis-programmed applications that >have grown to depend on unused MOCS entries, we are programming >those entries to be equal to fully cached ("L3 + LLC") entry. > >These reserved and unspecified entries should not be used as they may be >changed to less performant variants with better coherency in the future >if more entries are needed. > >Cc: Chris Wilson <chris@chris-wilson.co.uk> >Cc: Lucas De Marchi <lucas.demarchi@intel.com> >Cc: Tomasz Lis <tomasz.lis@intel.com> >Cc: Matt Roper <matthew.d.roper@intel.com> >Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> >Cc: Francisco Jerez <currojerez@riseup.net> >Cc: Mathew, Alwin <alwin.mathew@intel.com> >Cc: Mcguire, Russell W <russell.w.mcguire@intel.com> >Cc: Spruit, Neil R <neil.r.spruit@intel.com> >Cc: Zhou, Cheng <cheng.zhou@intel.com> >Cc: Benemelis, Mike G <mike.g.benemelis@intel.com> > >Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com> >--- > drivers/gpu/drm/i915/gt/intel_mocs.c | 93 ++++++++++++++++++++++++++-- > 1 file changed, 89 insertions(+), 4 deletions(-) > >diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c >index 632e08a4592b2..1089bd5fdba2c 100644 >--- a/drivers/gpu/drm/i915/gt/intel_mocs.c >+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c >@@ -234,10 +234,6 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = { > L3_1_UC) > > static const struct drm_i915_mocs_entry tgl_mocs_table[] = { >- /* Base - Error (Reserved for Non-Use) */ >- MOCS_ENTRY(0, 0x0, 0x0), >- /* Base - Reserved */ >- MOCS_ENTRY(1, 0x0, 0x0), > > GEN11_MOCS_ENTRIES, > >@@ -265,6 +261,95 @@ static const struct drm_i915_mocs_entry tgl_mocs_table[] = { > MOCS_ENTRY(61, > LE_1_UC | LE_TC_1_LLC, > L3_3_WB), >+ >+ /* NOTE: >+ * Reserved and unspecified MOCS indices have been set to (L3 + LCC). >+ * These reserved entry should never be used, they may be chanaged >+ * to low performant variants with better coherency in the future if >+ * more entries are needed. >+ */ the whole point of structing this table the way it is is that it doesn't take more space than needed and we can override values from previous platforms. MOCS_ENTRY() will set .used = 1. It seems that what you want is to actually change the value when .used == 0 is set. It seems you actually want to set the unused ones to that specific value. See __init_mocs_table() Lucas De Marchi >+ >+ /* Reserved index 0 and 1 */ >+ MOCS_ENTRY(0, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(1, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ >+ /* Reserved index 16 and 17 */ >+ MOCS_ENTRY(16, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(17, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ >+ /* Reserved index 24 and 25 */ >+ MOCS_ENTRY(24, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(25, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ >+ /* Unspecified indices 26 to 47 */ >+ MOCS_ENTRY(26, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(27, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(28, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(29, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(30, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(31, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(32, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(33, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(34, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(35, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(36, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(37, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(38, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(39, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(40, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(41, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(42, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(43, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(44, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(45, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(46, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(47, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ >+ /* Unspecified indices 52 to 59 */ >+ MOCS_ENTRY(52, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(53, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(54, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(55, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(56, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(57, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(58, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(59, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB) > }; > > static const struct drm_i915_mocs_entry icl_mocs_table[] = { >-- >2.26.2 > >_______________________________________________ >Intel-gfx mailing list >Intel-gfx@lists.freedesktop.org >https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 632e08a4592b2..1089bd5fdba2c 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -234,10 +234,6 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = { L3_1_UC) static const struct drm_i915_mocs_entry tgl_mocs_table[] = { - /* Base - Error (Reserved for Non-Use) */ - MOCS_ENTRY(0, 0x0, 0x0), - /* Base - Reserved */ - MOCS_ENTRY(1, 0x0, 0x0), GEN11_MOCS_ENTRIES, @@ -265,6 +261,95 @@ static const struct drm_i915_mocs_entry tgl_mocs_table[] = { MOCS_ENTRY(61, LE_1_UC | LE_TC_1_LLC, L3_3_WB), + + /* NOTE: + * Reserved and unspecified MOCS indices have been set to (L3 + LCC). + * These reserved entry should never be used, they may be chanaged + * to low performant variants with better coherency in the future if + * more entries are needed. + */ + + /* Reserved index 0 and 1 */ + MOCS_ENTRY(0, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(1, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + + /* Reserved index 16 and 17 */ + MOCS_ENTRY(16, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(17, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + + /* Reserved index 24 and 25 */ + MOCS_ENTRY(24, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(25, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + + /* Unspecified indices 26 to 47 */ + MOCS_ENTRY(26, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(27, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(28, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(29, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(30, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(31, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(32, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(33, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(34, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(35, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(36, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(37, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(38, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(39, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(40, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(41, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(42, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(43, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(44, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(45, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(46, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(47, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + + /* Unspecified indices 52 to 59 */ + MOCS_ENTRY(52, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(53, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(54, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(55, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(56, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(57, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(58, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(59, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB) }; static const struct drm_i915_mocs_entry icl_mocs_table[] = {
In order to avoid functional breakage of mis-programmed applications that have grown to depend on unused MOCS entries, we are programming those entries to be equal to fully cached ("L3 + LLC") entry. These reserved and unspecified entries should not be used as they may be changed to less performant variants with better coherency in the future if more entries are needed. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Tomasz Lis <tomasz.lis@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Francisco Jerez <currojerez@riseup.net> Cc: Mathew, Alwin <alwin.mathew@intel.com> Cc: Mcguire, Russell W <russell.w.mcguire@intel.com> Cc: Spruit, Neil R <neil.r.spruit@intel.com> Cc: Zhou, Cheng <cheng.zhou@intel.com> Cc: Benemelis, Mike G <mike.g.benemelis@intel.com> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com> --- drivers/gpu/drm/i915/gt/intel_mocs.c | 93 ++++++++++++++++++++++++++-- 1 file changed, 89 insertions(+), 4 deletions(-)