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bh=t/T/N8+T8VRdD2pd3O+kasRwWgBFC0Eh4uFuB6FWblI=; b=GnBl9HfIf9AXudsPOw1Qmt04dbYcfUnT/anaH3nP0dnZArYbXGB7WfAKNK9DOIFzXh sCIVTfBgsYcmhG86R22fDc984FKsgcXgYQWbqL2oZC4JMmzVaCWcpd5dj5kwSg0B8f9H bSVRUlRp9FOZp80PdQ90DKngPbYtsAsE09yhOFhKUuHW8RJIWjY+ydAzcfSF+MTI87JR 0vZY0bFh7sPTCjSl9168TzCUbqPKF+ocPVmgIUPWVIaR0zJUIsYNMyNUyGjgISeUDMrT 2z+RdvD3VKj3ptyqKFKL6N1WZPKaC232MUoI4ksNzfkgBRbWvxZmg4dShr6yRRmd8rj3 55Cw== X-Gm-Message-State: AOAM533rusp+Gh62aOnJNNYLxp/ieInRt4zdT7h52bCtWZzuH8ztjF7/ cOMQyw2pua+J7E/gZqyvjT7Io5Gn X-Google-Smtp-Source: ABdhPJwwCBDuUrdAtcpI4eEVifkWpvyoLlDNFzmhdcJKoqs7+myVuPLRwYJLFiikdQHsX+p6HaofpA== X-Received: by 2002:a65:6089:: with SMTP id t9mr21707464pgu.236.1592996682708; Wed, 24 Jun 2020 04:04:42 -0700 (PDT) Received: from localhost.localdomain ([103.51.74.220]) by smtp.gmail.com with ESMTPSA id s98sm5272796pjb.33.2020.06.24.04.04.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jun 2020 04:04:42 -0700 (PDT) From: Anand Moon To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Marek Szyprowski , Bartlomiej Zolnierkiewicz Subject: [PATCH] ARM: dts: exynos: Fix L2 cache-controller nodename Date: Wed, 24 Jun 2020 11:04:35 +0000 Message-Id: <20200624110435.1150-1-linux.amoon@gmail.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Fix warning message by changing nodename to 'cache-controller'. make ARCH=arm dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/arm/l2c2x0.yaml arch/arm/boot/dts/exynos4210-i9100.dt.yaml: l2-cache-controller@10502000: $nodename:0: 'l2-cache-controller@10502000' does not match ' ^(cache-controller|cpu)(@[0-9a-f,]+)*$' arch/arm/boot/dts/exynos4412-i9300.dt.yaml: l2-cache-controller@10502000: $nodename:0: 'l2-cache-controller@10502000' does not match ' ^(cache-controller|cpu)(@[0-9a-f,]+)*$' Fixes: 56b60b8bce4a ("ARM: 8265/1: dts: exynos4: Add nodes for L2 cache controller") Signed-off-by: Anand Moon --- arch/arm/boot/dts/exynos4210.dtsi | 2 +- arch/arm/boot/dts/exynos4412.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index b4466232f0c1..33435ce79ce4 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -97,7 +97,7 @@ pd_lcd1: power-domain@10023ca0 { label = "LCD1"; }; - l2c: l2-cache-controller@10502000 { + l2c: cache-controller@10502000 { compatible = "arm,pl310-cache"; reg = <0x10502000 0x1000>; cache-unified; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 48868947373e..7002832eb4c0 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -213,7 +213,7 @@ pd_isp: power-domain@10023ca0 { label = "ISP"; }; - l2c: l2-cache-controller@10502000 { + l2c: cache-controller@10502000 { compatible = "arm,pl310-cache"; reg = <0x10502000 0x1000>; cache-unified;