diff mbox series

[v2,6/7] arm64: dts: mt8183: Add USB3.0 support

Message ID 20200625101757.101775-7-enric.balletbo@collabora.com (mailing list archive)
State Mainlined
Commit 6b3bfa37a90a373baf01ebb97ff4200f4d56d886
Headers show
Series arm64: dts: mediatek: Add support for Lenovo IdeaPad Duet Chromebook | expand

Commit Message

Enric Balletbo i Serra June 25, 2020, 10:17 a.m. UTC 
Add the USB3.0 phyter and controller for the MediaTek's MT8183 SoC.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---

Changes in v2:
- Move adding #phy-cells to this patch. (Matthias Brugger)

 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 58 ++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

Comments

Hsin-Yi Wang July 2, 2020, 5:06 a.m. UTC | #1 
On Thu, Jun 25, 2020 at 6:18 PM Enric Balletbo i Serra
<enric.balletbo@collabora.com> wrote:
>
> Add the USB3.0 phyter and controller for the MediaTek's MT8183 SoC.
>
> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Tested-by: Hsin-Yi Wang <hsinyi@chromium.org>
> ---
>
> Changes in v2:
> - Move adding #phy-cells to this patch. (Matthias Brugger)
>
>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 58 ++++++++++++++++++++++++
>  1 file changed, 58 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 6c00ffa275202..102105871db25 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -9,6 +9,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/reset-controller/mt8183-resets.h>
> +#include <dt-bindings/phy/phy.h>
>  #include "mt8183-pinfunc.h"
>
>  / {
> @@ -648,6 +649,36 @@ i2c8: i2c@1101b000 {
>                         status = "disabled";
>                 };
>
> +               ssusb: usb@11201000 {
> +                       compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3";
> +                       reg = <0 0x11201000 0 0x2e00>,
> +                             <0 0x11203e00 0 0x0100>;
> +                       reg-names = "mac", "ippc";
> +                       interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
> +                       phys = <&u2port0 PHY_TYPE_USB2>,
> +                              <&u3port0 PHY_TYPE_USB3>;
> +                       clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
> +                                <&infracfg CLK_INFRA_USB>;
> +                       clock-names = "sys_ck", "ref_ck";
> +                       mediatek,syscon-wakeup = <&pericfg 0x400 0>;
> +                       #address-cells = <2>;
> +                       #size-cells = <2>;
> +                       ranges;
> +                       status = "disabled";
> +
> +                       usb_host: xhci@11200000 {
> +                               compatible = "mediatek,mt8183-xhci",
> +                                            "mediatek,mtk-xhci";
> +                               reg = <0 0x11200000 0 0x1000>;
> +                               reg-names = "mac";
> +                               interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
> +                               clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
> +                                        <&infracfg CLK_INFRA_USB>;
> +                               clock-names = "sys_ck", "ref_ck";
> +                               status = "disabled";
> +                       };
> +               };
> +
>                 audiosys: syscon@11220000 {
>                         compatible = "mediatek,mt8183-audiosys", "syscon";
>                         reg = <0 0x11220000 0 0x1000>;
> @@ -684,6 +715,33 @@ efuse: efuse@11f10000 {
>                         reg = <0 0x11f10000 0 0x1000>;
>                 };
>
> +               u3phy: usb-phy@11f40000 {
> +                       compatible = "mediatek,mt8183-tphy",
> +                                    "mediatek,generic-tphy-v2";
> +                       #address-cells = <1>;
> +                       #phy-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges = <0 0 0x11f40000 0x1000>;
> +                       status = "okay";
> +
> +                       u2port0: usb-phy@0 {
> +                               reg = <0x0 0x700>;
> +                               clocks = <&clk26m>;
> +                               clock-names = "ref";
> +                               #phy-cells = <1>;
> +                               mediatek,discth = <15>;
> +                               status = "okay";
> +                       };
> +
> +                       u3port0: usb-phy@0700 {
> +                               reg = <0x0700 0x900>;
> +                               clocks = <&clk26m>;
> +                               clock-names = "ref";
> +                               #phy-cells = <1>;
> +                               status = "okay";
> +                       };
> +               };
> +
>                 mfgcfg: syscon@13000000 {
>                         compatible = "mediatek,mt8183-mfgcfg", "syscon";
>                         reg = <0 0x13000000 0 0x1000>;
> --
> 2.27.0
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 6c00ffa275202..102105871db25 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -9,6 +9,7 @@ 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/reset-controller/mt8183-resets.h>
+#include <dt-bindings/phy/phy.h>
 #include "mt8183-pinfunc.h"
 
 / {
@@ -648,6 +649,36 @@  i2c8: i2c@1101b000 {
 			status = "disabled";
 		};
 
+		ssusb: usb@11201000 {
+			compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3";
+			reg = <0 0x11201000 0 0x2e00>,
+			      <0 0x11203e00 0 0x0100>;
+			reg-names = "mac", "ippc";
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
+			phys = <&u2port0 PHY_TYPE_USB2>,
+			       <&u3port0 PHY_TYPE_USB3>;
+			clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
+				 <&infracfg CLK_INFRA_USB>;
+			clock-names = "sys_ck", "ref_ck";
+			mediatek,syscon-wakeup = <&pericfg 0x400 0>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			status = "disabled";
+
+			usb_host: xhci@11200000 {
+				compatible = "mediatek,mt8183-xhci",
+					     "mediatek,mtk-xhci";
+				reg = <0 0x11200000 0 0x1000>;
+				reg-names = "mac";
+				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
+				clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
+					 <&infracfg CLK_INFRA_USB>;
+				clock-names = "sys_ck", "ref_ck";
+				status = "disabled";
+			};
+		};
+
 		audiosys: syscon@11220000 {
 			compatible = "mediatek,mt8183-audiosys", "syscon";
 			reg = <0 0x11220000 0 0x1000>;
@@ -684,6 +715,33 @@  efuse: efuse@11f10000 {
 			reg = <0 0x11f10000 0 0x1000>;
 		};
 
+		u3phy: usb-phy@11f40000 {
+			compatible = "mediatek,mt8183-tphy",
+				     "mediatek,generic-tphy-v2";
+			#address-cells = <1>;
+			#phy-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0 0x11f40000 0x1000>;
+			status = "okay";
+
+			u2port0: usb-phy@0 {
+				reg = <0x0 0x700>;
+				clocks = <&clk26m>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+				mediatek,discth = <15>;
+				status = "okay";
+			};
+
+			u3port0: usb-phy@0700 {
+				reg = <0x0700 0x900>;
+				clocks = <&clk26m>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+				status = "okay";
+			};
+		};
+
 		mfgcfg: syscon@13000000 {
 			compatible = "mediatek,mt8183-mfgcfg", "syscon";
 			reg = <0 0x13000000 0 0x1000>;