[v1] drm/msm/dpu: enumerate second cursor pipe for external interface
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Message ID 1593089153-17811-1-git-send-email-kalyan_t@codeaurora.org
State New
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Series
  • [v1] drm/msm/dpu: enumerate second cursor pipe for external interface
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Commit Message

Kalyan Thota June 25, 2020, 12:45 p.m. UTC
Setup an RGB HW pipe as cursor which can be used on
secondary interface.

For SC7180 2 HW pipes are enumerated as cursors
1 - primary interface
2 - secondary interface

Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

Comments

Rob Clark July 10, 2020, 4:49 p.m. UTC | #1
On Thu, Jun 25, 2020 at 5:46 AM Kalyan Thota <kalyan_t@codeaurora.org> wrote:
>
> Setup an RGB HW pipe as cursor which can be used on
> secondary interface.
>
> For SC7180 2 HW pipes are enumerated as cursors
> 1 - primary interface
> 2 - secondary interface
>
> Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 8f2357d..23061fd 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -117,10 +117,10 @@
>                 .reg_off = 0x2AC, .bit_off = 0},
>         .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
>                 .reg_off = 0x2AC, .bit_off = 8},
> -       .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
> -               .reg_off = 0x2B4, .bit_off = 8},
>         .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
> -               .reg_off = 0x2BC, .bit_off = 8},
> +               .reg_off = 0x2B4, .bit_off = 8},
> +       .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
> +               .reg_off = 0x2C4, .bit_off = 8},

It looks like you shifted the register offset here from 0x2bc to
0x2c4, was that intentional?

BR,
-R

>         },
>  };
>
> @@ -272,10 +272,10 @@
>                 sc7180_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>         SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
>                 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> -       SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_SDM845_MASK,
> -               sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> +       SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_CURSOR_SDM845_MASK,
> +               sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
>         SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000,  DMA_CURSOR_SDM845_MASK,
> -               sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
> +               sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
>  };
>
>  /*************************************************************
> --
> 1.9.1
>
Kalyan Thota July 13, 2020, 10:18 a.m. UTC | #2
On 2020-07-10 22:19, Rob Clark wrote:
> On Thu, Jun 25, 2020 at 5:46 AM Kalyan Thota <kalyan_t@codeaurora.org> 
> wrote:
>> 
>> Setup an RGB HW pipe as cursor which can be used on
>> secondary interface.
>> 
>> For SC7180 2 HW pipes are enumerated as cursors
>> 1 - primary interface
>> 2 - secondary interface
>> 
>> Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org>
>> ---
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 12 ++++++------
>>  1 file changed, 6 insertions(+), 6 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index 8f2357d..23061fd 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -117,10 +117,10 @@
>>                 .reg_off = 0x2AC, .bit_off = 0},
>>         .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
>>                 .reg_off = 0x2AC, .bit_off = 8},
>> -       .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
>> -               .reg_off = 0x2B4, .bit_off = 8},
>>         .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
>> -               .reg_off = 0x2BC, .bit_off = 8},
>> +               .reg_off = 0x2B4, .bit_off = 8},
>> +       .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
>> +               .reg_off = 0x2C4, .bit_off = 8},
> 
> It looks like you shifted the register offset here from 0x2bc to
> 0x2c4, was that intentional?
> 
> BR,
> -R
Yes Rob, the offset was wrong which i corrected in this patch.
> 
>>         },
>>  };
>> 
>> @@ -272,10 +272,10 @@
>>                 sc7180_vig_sblk_0, 0,  SSPP_TYPE_VIG, 
>> DPU_CLK_CTRL_VIG0),
>>         SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
>>                 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, 
>> DPU_CLK_CTRL_DMA0),
>> -       SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_SDM845_MASK,
>> -               sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, 
>> DPU_CLK_CTRL_DMA1),
>> +       SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  
>> DMA_CURSOR_SDM845_MASK,
>> +               sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, 
>> DPU_CLK_CTRL_CURSOR0),
>>         SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000,  
>> DMA_CURSOR_SDM845_MASK,
>> -               sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, 
>> DPU_CLK_CTRL_CURSOR0),
>> +               sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, 
>> DPU_CLK_CTRL_CURSOR1),
>>  };
>> 
>>  /*************************************************************
>> --
>> 1.9.1
>> 
> _______________________________________________
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> Freedreno@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/freedreno
Rob Clark July 13, 2020, 2:14 p.m. UTC | #3
On Mon, Jul 13, 2020 at 3:18 AM <kalyan_t@codeaurora.org> wrote:
>
> On 2020-07-10 22:19, Rob Clark wrote:
> > On Thu, Jun 25, 2020 at 5:46 AM Kalyan Thota <kalyan_t@codeaurora.org>
> > wrote:
> >>
> >> Setup an RGB HW pipe as cursor which can be used on
> >> secondary interface.
> >>
> >> For SC7180 2 HW pipes are enumerated as cursors
> >> 1 - primary interface
> >> 2 - secondary interface
> >>
> >> Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org>
> >> ---
> >>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 12 ++++++------
> >>  1 file changed, 6 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >> index 8f2357d..23061fd 100644
> >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >> @@ -117,10 +117,10 @@
> >>                 .reg_off = 0x2AC, .bit_off = 0},
> >>         .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
> >>                 .reg_off = 0x2AC, .bit_off = 8},
> >> -       .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
> >> -               .reg_off = 0x2B4, .bit_off = 8},
> >>         .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
> >> -               .reg_off = 0x2BC, .bit_off = 8},
> >> +               .reg_off = 0x2B4, .bit_off = 8},
> >> +       .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
> >> +               .reg_off = 0x2C4, .bit_off = 8},
> >
> > It looks like you shifted the register offset here from 0x2bc to
> > 0x2c4, was that intentional?
> >
> > BR,
> > -R
> Yes Rob, the offset was wrong which i corrected in this patch.


Thanks for confirming.  In the future, it would have been useful to
mention that in the commit msg.

BR,
-R

Patch
diff mbox series

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 8f2357d..23061fd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -117,10 +117,10 @@ 
 		.reg_off = 0x2AC, .bit_off = 0},
 	.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
 		.reg_off = 0x2AC, .bit_off = 8},
-	.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
-		.reg_off = 0x2B4, .bit_off = 8},
 	.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
-		.reg_off = 0x2BC, .bit_off = 8},
+		.reg_off = 0x2B4, .bit_off = 8},
+	.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
+		.reg_off = 0x2C4, .bit_off = 8},
 	},
 };
 
@@ -272,10 +272,10 @@ 
 		sc7180_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
 	SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
 		sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
-	SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_SDM845_MASK,
-		sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
+	SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_CURSOR_SDM845_MASK,
+		sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
 	SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000,  DMA_CURSOR_SDM845_MASK,
-		sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
+		sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
 };
 
 /*************************************************************