diff mbox series

[v2,1/3] clk: JZ4780: Add functions for enable and disable USB PHY.

Message ID 20200628171543.51478-2-zhouyanjie@wanyeetech.com (mailing list archive)
State Superseded, archived
Headers show
Series Add functions to operate USB PHY related clock. | expand

Commit Message

Zhou Yanjie June 28, 2020, 5:15 p.m. UTC 
Add new functions to "jz4780_otg_phy_ops" to enable or disable the
USB PHY in the JZ4780 SoC.

Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---

Notes:
    v1->v2:
    1.Use "WARN()" instead "BUG()".
    2.Move the reformat part ot the new patch.
    3.Remove unnecessary get_parent/set_parent functions.

 drivers/clk/ingenic/jz4780-cgu.c | 67 ++++++++++++++++++++++------------------
 1 file changed, 37 insertions(+), 30 deletions(-)

Comments

kernel test robot June 29, 2020, 9:28 a.m. UTC | #1 
Hi "周琰杰,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on clk/clk-next]
[also build test ERROR on linux/master linus/master v5.8-rc3 next-20200629]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use  as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Zhou-Yanjie/Add-functions-to-operate-USB-PHY-related-clock/20200629-011858
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: alpha-allyesconfig (attached as .config)
compiler: alpha-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=alpha 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All error/warnings (new ones prefixed by >>):

   In file included from arch/alpha/include/asm/bug.h:23,
                    from include/linux/bug.h:5,
                    from include/linux/thread_info.h:12,
                    from include/asm-generic/current.h:5,
                    from ./arch/alpha/include/generated/asm/current.h:1,
                    from include/linux/mutex.h:14,
                    from include/linux/kernfs.h:12,
                    from include/linux/sysfs.h:16,
                    from include/linux/kobject.h:20,
                    from include/linux/of.h:17,
                    from include/linux/clk-provider.h:9,
                    from drivers/clk/ingenic/jz4780-cgu.c:10:
   drivers/clk/ingenic/jz4780-cgu.c: In function 'jz4780_otg_phy_recalc_rate':
>> include/asm-generic/bug.h:127:34: error: expected expression before ')' token
     127 |  int __ret_warn_on = !!(condition);    \
         |                                  ^
>> drivers/clk/ingenic/jz4780-cgu.c:129:2: note: in expansion of macro 'WARN'
     129 |  WARN();
         |  ^~~~
   include/asm-generic/bug.h:88:51: error: expected expression before ')' token
      88 |   warn_slowpath_fmt(__FILE__, __LINE__, taint, arg); \
         |                                                   ^
   include/asm-generic/bug.h:129:3: note: in expansion of macro '__WARN_printf'
     129 |   __WARN_printf(TAINT_WARN, format);   \
         |   ^~~~~~~~~~~~~
>> drivers/clk/ingenic/jz4780-cgu.c:129:2: note: in expansion of macro 'WARN'
     129 |  WARN();
         |  ^~~~

vim +/WARN +129 drivers/clk/ingenic/jz4780-cgu.c

   105	
   106	static unsigned long jz4780_otg_phy_recalc_rate(struct clk_hw *hw,
   107							unsigned long parent_rate)
   108	{
   109		u32 usbpcr1;
   110		unsigned refclk_div;
   111	
   112		usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
   113		refclk_div = usbpcr1 & USBPCR1_REFCLKDIV_MASK;
   114	
   115		switch (refclk_div) {
   116		case USBPCR1_REFCLKDIV_12:
   117			return 12000000;
   118	
   119		case USBPCR1_REFCLKDIV_24:
   120			return 24000000;
   121	
   122		case USBPCR1_REFCLKDIV_48:
   123			return 48000000;
   124	
   125		case USBPCR1_REFCLKDIV_19_2:
   126			return 19200000;
   127		}
   128	
 > 129		WARN();
   130		return parent_rate;
   131	}
   132	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
diff mbox series

Patch

diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c
index 6c5b8029cc8a..e2e43bfe9697 100644
--- a/drivers/clk/ingenic/jz4780-cgu.c
+++ b/drivers/clk/ingenic/jz4780-cgu.c
@@ -4,6 +4,7 @@ 
  *
  * Copyright (c) 2013-2015 Imagination Technologies
  * Author: Paul Burton <paul.burton@mips.com>
+ * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
  */
 
 #include <linux/clk-provider.h>
@@ -59,6 +60,7 @@ 
 #define USBPCR_VBUSVLDEXT	BIT(24)
 #define USBPCR_VBUSVLDEXTSEL	BIT(23)
 #define USBPCR_POR		BIT(22)
+#define USBPCR_SIDDQ		BIT(21)
 #define USBPCR_OTG_DISABLE	BIT(20)
 #define USBPCR_COMPDISTUNE_MASK	(0x7 << 17)
 #define USBPCR_OTGTUNE_MASK	(0x7 << 14)
@@ -68,6 +70,7 @@ 
 #define USBPCR_TXHSXVTUNE_MASK	(0x3 << 4)
 #define USBPCR_TXVREFTUNE_MASK	0xf
 
+
 /* bits within the USBPCR1 register */
 #define USBPCR1_REFCLKSEL_SHIFT	26
 #define USBPCR1_REFCLKSEL_MASK	(0x3 << USBPCR1_REFCLKSEL_SHIFT)
@@ -100,32 +103,6 @@ 
 
 static struct ingenic_cgu *cgu;
 
-static u8 jz4780_otg_phy_get_parent(struct clk_hw *hw)
-{
-	/* we only use CLKCORE, revisit if that ever changes */
-	return 0;
-}
-
-static int jz4780_otg_phy_set_parent(struct clk_hw *hw, u8 idx)
-{
-	unsigned long flags;
-	u32 usbpcr1;
-
-	if (idx > 0)
-		return -EINVAL;
-
-	spin_lock_irqsave(&cgu->lock, flags);
-
-	usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
-	usbpcr1 &= ~USBPCR1_REFCLKSEL_MASK;
-	/* we only use CLKCORE */
-	usbpcr1 |= USBPCR1_REFCLKSEL_CORE;
-	writel(usbpcr1, cgu->base + CGU_REG_USBPCR1);
-
-	spin_unlock_irqrestore(&cgu->lock, flags);
-	return 0;
-}
-
 static unsigned long jz4780_otg_phy_recalc_rate(struct clk_hw *hw,
 						unsigned long parent_rate)
 {
@@ -149,7 +126,7 @@  static unsigned long jz4780_otg_phy_recalc_rate(struct clk_hw *hw,
 		return 19200000;
 	}
 
-	BUG();
+	WARN();
 	return parent_rate;
 }
 
@@ -206,13 +183,43 @@  static int jz4780_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate,
 	return 0;
 }
 
-static const struct clk_ops jz4780_otg_phy_ops = {
-	.get_parent = jz4780_otg_phy_get_parent,
-	.set_parent = jz4780_otg_phy_set_parent,
+static int jz4780_otg_phy_enable(struct clk_hw *hw)
+{
+	void __iomem *reg_opcr		= cgu->base + CGU_REG_OPCR;
+	void __iomem *reg_usbpcr	= cgu->base + CGU_REG_USBPCR;
+
+	writel(readl(reg_opcr) | OPCR_SPENDN0, reg_opcr);
+	writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr);
+	return 0;
+}
+
+static void jz4780_otg_phy_disable(struct clk_hw *hw)
+{
+	void __iomem *reg_opcr		= cgu->base + CGU_REG_OPCR;
+	void __iomem *reg_usbpcr	= cgu->base + CGU_REG_USBPCR;
 
+	writel(readl(reg_opcr) & ~OPCR_SPENDN0, reg_opcr);
+	writel(readl(reg_usbpcr) | USBPCR_OTG_DISABLE | USBPCR_SIDDQ, reg_usbpcr);
+}
+
+static int jz4780_otg_phy_is_enabled(struct clk_hw *hw)
+{
+	void __iomem *reg_opcr		= cgu->base + CGU_REG_OPCR;
+	void __iomem *reg_usbpcr	= cgu->base + CGU_REG_USBPCR;
+
+	return (readl(reg_opcr) & OPCR_SPENDN0) &&
+		!(readl(reg_usbpcr) & USBPCR_SIDDQ) &&
+		!(readl(reg_usbpcr) & USBPCR_OTG_DISABLE);
+}
+
+static const struct clk_ops jz4780_otg_phy_ops = {
 	.recalc_rate = jz4780_otg_phy_recalc_rate,
 	.round_rate = jz4780_otg_phy_round_rate,
 	.set_rate = jz4780_otg_phy_set_rate,
+
+	.enable		= jz4780_otg_phy_enable,
+	.disable	= jz4780_otg_phy_disable,
+	.is_enabled	= jz4780_otg_phy_is_enabled,
 };
 
 static int jz4780_core1_enable(struct clk_hw *hw)