| Message ID | 20200629071310.1557-5-chao.hao@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | MT6779 IOMMU SUPPORT | expand |
On 29/06/2020 09:13, Chao Hao wrote: > Add F_MMU_IN_ORDER_WR_EN and F_MMU_STANDARD_AXI_MODE_BIT definition > in MISC_CTRL register. > F_MMU_STANDARD_AXI_MODE_BIT: > If we set F_MMU_STANDARD_AXI_MODE_BIT(bit[3][19] = 0, not follow > standard AXI protocol), iommu will send urgent read command firstly > compare with normal read command to improve performance. Can you please help me to understand the phrase. Sorry I'm not a AXI specialist. Does this mean that you will send a 'urgent read command' which is not described in the specifications instead of a normal read command? > F_MMU_IN_ORDER_WR_EN: > If we set F_MMU_IN_ORDER_WR_EN(bit[1][17] = 0, out-of-order write), iommu > will re-order write command and send more higher priority write command > instead of sending write command in order. The feature be controlled > by OUT_ORDER_EN macro definition. > > Cc: Matthias Brugger <matthias.bgg@gmail.com> > Suggested-by: Yong Wu <yong.wu@mediatek.com> > Signed-off-by: Chao Hao <chao.hao@mediatek.com> > --- > drivers/iommu/mtk_iommu.c | 12 +++++++++++- > drivers/iommu/mtk_iommu.h | 1 + > 2 files changed, 12 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 8f81df6cbe51..67b46b5d83d9 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -42,6 +42,9 @@ > #define F_INVLD_EN1 BIT(1) > > #define REG_MMU_MISC_CTRL 0x048 > +#define F_MMU_IN_ORDER_WR_EN (BIT(1) | BIT(17)) > +#define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19)) Wouldn't it make more sense to name it F_MMU_STANDARD_AXI_MODE_EN? > + > #define REG_MMU_DCM_DIS 0x050 > > #define REG_MMU_CTRL_REG 0x110 > @@ -574,10 +577,17 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > } > writel_relaxed(0, data->base + REG_MMU_DCM_DIS); > > + regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); We only need to read regval in the else branch. > if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { > /* The register is called STANDARD_AXI_MODE in this case */ > - writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); > + regval = 0; > + } else { > + /* For mm_iommu, it can improve performance by the setting */ > + regval &= ~F_MMU_STANDARD_AXI_MODE_BIT; > + if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_EN)) > + regval &= ~F_MMU_IN_ORDER_WR_EN; > } > + writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); > > if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, > dev_name(data->dev), (void *)data)) { > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h > index 7cc39f729263..4b780b651ef4 100644 > --- a/drivers/iommu/mtk_iommu.h > +++ b/drivers/iommu/mtk_iommu.h > @@ -22,6 +22,7 @@ > #define HAS_BCLK BIT(1) > #define HAS_VLD_PA_RNG BIT(2) > #define RESET_AXI BIT(3) > +#define OUT_ORDER_EN BIT(4) Maybe something like OUT_ORDER_WR_EN, to make clear that it's about the the write path. > > #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ > ((((pdata)->flags) & (_x)) == (_x)) >
On Mon, 2020-06-29 at 11:28 +0200, Matthias Brugger wrote: > > On 29/06/2020 09:13, Chao Hao wrote: > > Add F_MMU_IN_ORDER_WR_EN and F_MMU_STANDARD_AXI_MODE_BIT definition > > in MISC_CTRL register. > > F_MMU_STANDARD_AXI_MODE_BIT: > > If we set F_MMU_STANDARD_AXI_MODE_BIT(bit[3][19] = 0, not follow > > standard AXI protocol), iommu will send urgent read command firstly > > compare with normal read command to improve performance. > > Can you please help me to understand the phrase. Sorry I'm not a AXI specialist. > Does this mean that you will send a 'urgent read command' which is not described > in the specifications instead of a normal read command? ok. iommu sends read command to next bus_node normally(we can name it to cmd1), when cmd1 isn't handled by next bus_node, iommu has a urgent read command is needed to be sent(we can name it to cmd2), iommu will send cmd2 and replace cmd1. So cmd2 is handled by next bus_node firstly and cmd2 will be handled secondly. But for standard AXI protocol, it will ignore the priority of read command and only be handled in order. So cmd2 is handled by next bus_node after cmd1 is done. > > > F_MMU_IN_ORDER_WR_EN: > > If we set F_MMU_IN_ORDER_WR_EN(bit[1][17] = 0, out-of-order write), iommu > > will re-order write command and send more higher priority write command > > instead of sending write command in order. The feature be controlled > > by OUT_ORDER_EN macro definition. > > > > Cc: Matthias Brugger <matthias.bgg@gmail.com> > > Suggested-by: Yong Wu <yong.wu@mediatek.com> > > Signed-off-by: Chao Hao <chao.hao@mediatek.com> > > --- > > drivers/iommu/mtk_iommu.c | 12 +++++++++++- > > drivers/iommu/mtk_iommu.h | 1 + > > 2 files changed, 12 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > > index 8f81df6cbe51..67b46b5d83d9 100644 > > --- a/drivers/iommu/mtk_iommu.c > > +++ b/drivers/iommu/mtk_iommu.c > > @@ -42,6 +42,9 @@ > > #define F_INVLD_EN1 BIT(1) > > > > #define REG_MMU_MISC_CTRL 0x048 > > +#define F_MMU_IN_ORDER_WR_EN (BIT(1) | BIT(17)) > > +#define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19)) > > Wouldn't it make more sense to name it F_MMU_STANDARD_AXI_MODE_EN? ok, you are right. 1'b1: follow standard axi protocol > > > + > > #define REG_MMU_DCM_DIS 0x050 > > > > #define REG_MMU_CTRL_REG 0x110 > > @@ -574,10 +577,17 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > > } > > writel_relaxed(0, data->base + REG_MMU_DCM_DIS); > > > > + regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); > > We only need to read regval in the else branch. ok, I got it. thanks > > > if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { > > /* The register is called STANDARD_AXI_MODE in this case */ > > - writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); > > + regval = 0; > > + } else { > > + /* For mm_iommu, it can improve performance by the setting */ > > + regval &= ~F_MMU_STANDARD_AXI_MODE_BIT; > > + if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_EN)) > > + regval &= ~F_MMU_IN_ORDER_WR_EN; > > } > > + writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); > > > > if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, > > dev_name(data->dev), (void *)data)) { > > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h > > index 7cc39f729263..4b780b651ef4 100644 > > --- a/drivers/iommu/mtk_iommu.h > > +++ b/drivers/iommu/mtk_iommu.h > > @@ -22,6 +22,7 @@ > > #define HAS_BCLK BIT(1) > > #define HAS_VLD_PA_RNG BIT(2) > > #define RESET_AXI BIT(3) > > +#define OUT_ORDER_EN BIT(4) > > Maybe something like OUT_ORDER_WR_EN, to make clear that it's about the the > write path. > ok, thanks for your advice. > > > > #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ > > ((((pdata)->flags) & (_x)) == (_x)) > >
On 30/06/2020 12:53, chao hao wrote: > On Mon, 2020-06-29 at 11:28 +0200, Matthias Brugger wrote: >> >> On 29/06/2020 09:13, Chao Hao wrote: >>> Add F_MMU_IN_ORDER_WR_EN and F_MMU_STANDARD_AXI_MODE_BIT definition >>> in MISC_CTRL register. >>> F_MMU_STANDARD_AXI_MODE_BIT: >>> If we set F_MMU_STANDARD_AXI_MODE_BIT(bit[3][19] = 0, not follow >>> standard AXI protocol), iommu will send urgent read command firstly >>> compare with normal read command to improve performance. >> >> Can you please help me to understand the phrase. Sorry I'm not a AXI specialist. >> Does this mean that you will send a 'urgent read command' which is not described >> in the specifications instead of a normal read command? > > ok. > iommu sends read command to next bus_node normally(we can name it to > cmd1), when cmd1 isn't handled by next bus_node, iommu has a urgent read > command is needed to be sent(we can name it to cmd2), iommu will send > cmd2 and replace cmd1. So cmd2 is handled by next bus_node firstly and > cmd2 will be handled secondly. > But for standard AXI protocol, it will ignore the priority of read > command and only be handled in order. So cmd2 is handled by next > bus_node after cmd1 is done. > Thanks. So I propose change this part of the commit message to something like: F_MMU_STANDARD_AXI_MODE_BIT: If we set F_MMU_STANDARD_AXI_MODE_EN_MASK (bit[3][19] = 0, not follow standard AXI protocol), the iommu will priorize sending of urgent read command over a normal read command. This improves the performance. >> >>> F_MMU_IN_ORDER_WR_EN: >>> If we set F_MMU_IN_ORDER_WR_EN(bit[1][17] = 0, out-of-order write), iommu >>> will re-order write command and send more higher priority write command >>> instead of sending write command in order. The feature be controlled >>> by OUT_ORDER_EN macro definition. F_MMU_IN_ORDER_WR_EN: If we set F_MMU_IN_ORDER_WR_EN_MASK (bit[1][17] = 0, out-of-order write), the iommu will re-order write commands and send the write command with higher priority. Otherwise the sending of write commands will be done in order. The feature is controlled by OUT_ORDER_WR_EN platform data flag. >>> >>> Cc: Matthias Brugger <matthias.bgg@gmail.com> >>> Suggested-by: Yong Wu <yong.wu@mediatek.com> >>> Signed-off-by: Chao Hao <chao.hao@mediatek.com> >>> --- >>> drivers/iommu/mtk_iommu.c | 12 +++++++++++- >>> drivers/iommu/mtk_iommu.h | 1 + >>> 2 files changed, 12 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c >>> index 8f81df6cbe51..67b46b5d83d9 100644 >>> --- a/drivers/iommu/mtk_iommu.c >>> +++ b/drivers/iommu/mtk_iommu.c >>> @@ -42,6 +42,9 @@ >>> #define F_INVLD_EN1 BIT(1) >>> >>> #define REG_MMU_MISC_CTRL 0x048 >>> +#define F_MMU_IN_ORDER_WR_EN (BIT(1) | BIT(17)) >>> +#define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19)) >> >> Wouldn't it make more sense to name it F_MMU_STANDARD_AXI_MODE_EN? > ok, you are right. > 1'b1: follow standard axi protocol > What about F_MMU_IN_ORDER_WR_EN_MASK F_MMU_STANDARD_AXI_MODE_EN_MASK Background is that we have to set/unset two bits to enable or disable the feature, so it's a mask we have to apply to the register. Regards, Matthias >> >>> + >>> #define REG_MMU_DCM_DIS 0x050 >>> >>> #define REG_MMU_CTRL_REG 0x110 >>> @@ -574,10 +577,17 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) >>> } >>> writel_relaxed(0, data->base + REG_MMU_DCM_DIS); >>> >>> + regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); >> >> We only need to read regval in the else branch. > > ok, I got it. thanks > >> >>> if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { >>> /* The register is called STANDARD_AXI_MODE in this case */ >>> - writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); >>> + regval = 0; >>> + } else { >>> + /* For mm_iommu, it can improve performance by the setting */ >>> + regval &= ~F_MMU_STANDARD_AXI_MODE_BIT; >>> + if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_EN)) >>> + regval &= ~F_MMU_IN_ORDER_WR_EN; >>> } >>> + writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); >>> >>> if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, >>> dev_name(data->dev), (void *)data)) { >>> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h >>> index 7cc39f729263..4b780b651ef4 100644 >>> --- a/drivers/iommu/mtk_iommu.h >>> +++ b/drivers/iommu/mtk_iommu.h >>> @@ -22,6 +22,7 @@ >>> #define HAS_BCLK BIT(1) >>> #define HAS_VLD_PA_RNG BIT(2) >>> #define RESET_AXI BIT(3) >>> +#define OUT_ORDER_EN BIT(4) >> >> Maybe something like OUT_ORDER_WR_EN, to make clear that it's about the the >> write path. >> > ok, thanks for your advice. > >>> >>> #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ >>> ((((pdata)->flags) & (_x)) == (_x)) >>> >
On Wed, 2020-07-01 at 16:58 +0200, Matthias Brugger wrote: > > On 30/06/2020 12:53, chao hao wrote: > > On Mon, 2020-06-29 at 11:28 +0200, Matthias Brugger wrote: > >> > >> On 29/06/2020 09:13, Chao Hao wrote: > >>> Add F_MMU_IN_ORDER_WR_EN and F_MMU_STANDARD_AXI_MODE_BIT definition > >>> in MISC_CTRL register. > >>> F_MMU_STANDARD_AXI_MODE_BIT: > >>> If we set F_MMU_STANDARD_AXI_MODE_BIT(bit[3][19] = 0, not follow > >>> standard AXI protocol), iommu will send urgent read command firstly > >>> compare with normal read command to improve performance. > >> > >> Can you please help me to understand the phrase. Sorry I'm not a AXI specialist. > >> Does this mean that you will send a 'urgent read command' which is not described > >> in the specifications instead of a normal read command? > > > > ok. > > iommu sends read command to next bus_node normally(we can name it to > > cmd1), when cmd1 isn't handled by next bus_node, iommu has a urgent read > > command is needed to be sent(we can name it to cmd2), iommu will send > > cmd2 and replace cmd1. So cmd2 is handled by next bus_node firstly and > > cmd2 will be handled secondly. > > But for standard AXI protocol, it will ignore the priority of read > > command and only be handled in order. So cmd2 is handled by next > > bus_node after cmd1 is done. > > > > Thanks. So I propose change this part of the commit message to something like: > F_MMU_STANDARD_AXI_MODE_BIT: > If we set F_MMU_STANDARD_AXI_MODE_EN_MASK (bit[3][19] = 0, not follow standard > AXI protocol), the iommu will priorize sending of urgent read command over a > normal read command. This improves the performance. > ok, thanks > >> > >>> F_MMU_IN_ORDER_WR_EN: > >>> If we set F_MMU_IN_ORDER_WR_EN(bit[1][17] = 0, out-of-order write), iommu > >>> will re-order write command and send more higher priority write command > >>> instead of sending write command in order. The feature be controlled > >>> by OUT_ORDER_EN macro definition. > > F_MMU_IN_ORDER_WR_EN: > If we set F_MMU_IN_ORDER_WR_EN_MASK (bit[1][17] = 0, out-of-order write), the > iommu will re-order write commands and send the write command with higher > priority. Otherwise the sending of write commands will be done in order. The > feature is controlled by OUT_ORDER_WR_EN platform data flag. > > > >>> > >>> Cc: Matthias Brugger <matthias.bgg@gmail.com> > >>> Suggested-by: Yong Wu <yong.wu@mediatek.com> > >>> Signed-off-by: Chao Hao <chao.hao@mediatek.com> > >>> --- > >>> drivers/iommu/mtk_iommu.c | 12 +++++++++++- > >>> drivers/iommu/mtk_iommu.h | 1 + > >>> 2 files changed, 12 insertions(+), 1 deletion(-) > >>> > >>> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > >>> index 8f81df6cbe51..67b46b5d83d9 100644 > >>> --- a/drivers/iommu/mtk_iommu.c > >>> +++ b/drivers/iommu/mtk_iommu.c > >>> @@ -42,6 +42,9 @@ > >>> #define F_INVLD_EN1 BIT(1) > >>> > >>> #define REG_MMU_MISC_CTRL 0x048 > >>> +#define F_MMU_IN_ORDER_WR_EN (BIT(1) | BIT(17)) > >>> +#define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19)) > >> > >> Wouldn't it make more sense to name it F_MMU_STANDARD_AXI_MODE_EN? > > ok, you are right. > > 1'b1: follow standard axi protocol > > > > What about > F_MMU_IN_ORDER_WR_EN_MASK > F_MMU_STANDARD_AXI_MODE_EN_MASK > > Background is that we have to set/unset two bits to enable or disable the > feature, so it's a mask we have to apply to the register. > ok, thanks for your advice > Regards, > Matthias > > >> > >>> + > >>> #define REG_MMU_DCM_DIS 0x050 > >>> > >>> #define REG_MMU_CTRL_REG 0x110 > >>> @@ -574,10 +577,17 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > >>> } > >>> writel_relaxed(0, data->base + REG_MMU_DCM_DIS); > >>> > >>> + regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); > >> > >> We only need to read regval in the else branch. > > > > ok, I got it. thanks > > > >> > >>> if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { > >>> /* The register is called STANDARD_AXI_MODE in this case */ > >>> - writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); > >>> + regval = 0; > >>> + } else { > >>> + /* For mm_iommu, it can improve performance by the setting */ > >>> + regval &= ~F_MMU_STANDARD_AXI_MODE_BIT; > >>> + if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_EN)) > >>> + regval &= ~F_MMU_IN_ORDER_WR_EN; > >>> } > >>> + writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); > >>> > >>> if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, > >>> dev_name(data->dev), (void *)data)) { > >>> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h > >>> index 7cc39f729263..4b780b651ef4 100644 > >>> --- a/drivers/iommu/mtk_iommu.h > >>> +++ b/drivers/iommu/mtk_iommu.h > >>> @@ -22,6 +22,7 @@ > >>> #define HAS_BCLK BIT(1) > >>> #define HAS_VLD_PA_RNG BIT(2) > >>> #define RESET_AXI BIT(3) > >>> +#define OUT_ORDER_EN BIT(4) > >> > >> Maybe something like OUT_ORDER_WR_EN, to make clear that it's about the the > >> write path. > >> > > ok, thanks for your advice. > > > >>> > >>> #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ > >>> ((((pdata)->flags) & (_x)) == (_x)) > >>> > >
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 8f81df6cbe51..67b46b5d83d9 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -42,6 +42,9 @@ #define F_INVLD_EN1 BIT(1) #define REG_MMU_MISC_CTRL 0x048 +#define F_MMU_IN_ORDER_WR_EN (BIT(1) | BIT(17)) +#define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19)) + #define REG_MMU_DCM_DIS 0x050 #define REG_MMU_CTRL_REG 0x110 @@ -574,10 +577,17 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) } writel_relaxed(0, data->base + REG_MMU_DCM_DIS); + regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { /* The register is called STANDARD_AXI_MODE in this case */ - writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); + regval = 0; + } else { + /* For mm_iommu, it can improve performance by the setting */ + regval &= ~F_MMU_STANDARD_AXI_MODE_BIT; + if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_EN)) + regval &= ~F_MMU_IN_ORDER_WR_EN; } + writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, dev_name(data->dev), (void *)data)) { diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index 7cc39f729263..4b780b651ef4 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h @@ -22,6 +22,7 @@ #define HAS_BCLK BIT(1) #define HAS_VLD_PA_RNG BIT(2) #define RESET_AXI BIT(3) +#define OUT_ORDER_EN BIT(4) #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ ((((pdata)->flags) & (_x)) == (_x))
Add F_MMU_IN_ORDER_WR_EN and F_MMU_STANDARD_AXI_MODE_BIT definition in MISC_CTRL register. F_MMU_STANDARD_AXI_MODE_BIT: If we set F_MMU_STANDARD_AXI_MODE_BIT(bit[3][19] = 0, not follow standard AXI protocol), iommu will send urgent read command firstly compare with normal read command to improve performance. F_MMU_IN_ORDER_WR_EN: If we set F_MMU_IN_ORDER_WR_EN(bit[1][17] = 0, out-of-order write), iommu will re-order write command and send more higher priority write command instead of sending write command in order. The feature be controlled by OUT_ORDER_EN macro definition. Cc: Matthias Brugger <matthias.bgg@gmail.com> Suggested-by: Yong Wu <yong.wu@mediatek.com> Signed-off-by: Chao Hao <chao.hao@mediatek.com> --- drivers/iommu/mtk_iommu.c | 12 +++++++++++- drivers/iommu/mtk_iommu.h | 1 + 2 files changed, 12 insertions(+), 1 deletion(-)