[07/59] drm/kmb: Set OUT_FORMAT_CFG register
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Message ID 1593552491-23698-8-git-send-email-anitha.chrisanthus@intel.com
State New
Headers show
Series
  • Add support for Keem Bay DRM driver
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Commit Message

Chrisanthus, Anitha June 30, 2020, 9:27 p.m. UTC
v2: code review changes
Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>
---
 drivers/gpu/drm/kmb/kmb_plane.c | 14 +++++++++++++-
 drivers/gpu/drm/kmb/kmb_regs.h  |  1 +
 2 files changed, 14 insertions(+), 1 deletion(-)

Patch
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diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c
index 886229a..f609283 100644
--- a/drivers/gpu/drm/kmb/kmb_plane.c
+++ b/drivers/gpu/drm/kmb/kmb_plane.c
@@ -228,7 +228,7 @@  static void kmb_plane_atomic_update(struct drm_plane *plane,
 	unsigned int dma_len;
 	struct kmb_plane *kmb_plane = to_kmb_plane(plane);
 	unsigned int dma_cfg;
-	unsigned int ctrl = 0, val = 0;
+	unsigned int ctrl = 0, val = 0, out_format = 0;
 	unsigned int src_w, src_h, crtc_x, crtc_y;
 	unsigned char plane_id = kmb_plane->id;
 
@@ -299,6 +299,18 @@  static void kmb_plane_atomic_update(struct drm_plane *plane,
 	/* enable DMA */
 	kmb_write(lcd, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg);
 
+	/* FIXME no doc on how to set output format - may need to change
+	 * this later
+	 */
+	if (val & LCD_LAYER_BGR_ORDER)
+		out_format |= LCD_OUTF_BGR_ORDER;
+	else if (val & LCD_LAYER_CRCB_ORDER)
+		out_format |= LCD_OUTF_CRCB_ORDER;
+	/* do not interleave RGB channels for mipi Tx compatibility */
+	out_format |= LCD_OUTF_MIPI_RGB_MODE;
+	/* pixel format from LCD_LAYER_CFG */
+	out_format |= ((val >> 9) & 0x1F);
+	kmb_write(lcd, LCD_OUT_FORMAT_CFG, out_format);
 }
 
 static const struct drm_plane_helper_funcs kmb_plane_helper_funcs = {
diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h
index 14466b8..299ab99 100644
--- a/drivers/gpu/drm/kmb/kmb_regs.h
+++ b/drivers/gpu/drm/kmb/kmb_regs.h
@@ -340,6 +340,7 @@ 
 #define LCD_OUTF_BGR_ORDER			  (1 << 5)
 #define LCD_OUTF_Y_ORDER			  (1 << 6)
 #define LCD_OUTF_CRCB_ORDER			  (1 << 7)
+#define LCD_OUTF_MIPI_RGB_MODE			  (1 << 18)
 
 #define LCD_HSYNC_WIDTH				(0x4 * 0x801)
 #define LCD_H_BACKPORCH				(0x4 * 0x802)