diff mbox series

[v4,02/11] target/ppc: Enable Power ISA 3.1

Message ID 20200701234344.91843-3-ljp@linux.ibm.com (mailing list archive)
State New, archived
Headers show
Series Add several Power ISA 3.1 32/64-bit vector instructions | expand

Commit Message

Lijun Pan July 1, 2020, 11:43 p.m. UTC 
This patch enables the Power ISA 3.1 in QEMU.

Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
v4: split to 01/11 and 02/11
v2: add Power ISA 3.1 flag

 target/ppc/cpu.h                | 2 +-
 target/ppc/translate_init.inc.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

Comments

David Gibson July 5, 2020, 9:08 a.m. UTC | #1 
On Wed, Jul 01, 2020 at 06:43:37PM -0500, Lijun Pan wrote:
> This patch enables the Power ISA 3.1 in QEMU.
> 
> Signed-off-by: Lijun Pan <ljp@linux.ibm.com>

Applied to ppc-for-5.2.

> ---
> v4: split to 01/11 and 02/11
> v2: add Power ISA 3.1 flag
> 
>  target/ppc/cpu.h                | 2 +-
>  target/ppc/translate_init.inc.c | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index a5e9c08dcc..ebb5a0811a 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -2201,7 +2201,7 @@ enum {
>                          PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
>                          PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
>                          PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
> -                        PPC2_ISA300)
> +                        PPC2_ISA300 | PPC2_ISA310)
>  };
>  
>  /*****************************************************************************/
> diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
> index 38cb773ab4..3f72310e60 100644
> --- a/target/ppc/translate_init.inc.c
> +++ b/target/ppc/translate_init.inc.c
> @@ -9206,7 +9206,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
>                          PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
>                          PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
>                          PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
> -                        PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
> +                        PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310;
>      pcc->msr_mask = (1ull << MSR_SF) |
>                      (1ull << MSR_HV) |
>                      (1ull << MSR_TM) |
diff mbox series

Patch

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index a5e9c08dcc..ebb5a0811a 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2201,7 +2201,7 @@  enum {
                         PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
                         PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
                         PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
-                        PPC2_ISA300)
+                        PPC2_ISA300 | PPC2_ISA310)
 };
 
 /*****************************************************************************/
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index 38cb773ab4..3f72310e60 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -9206,7 +9206,7 @@  POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
                         PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
                         PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
                         PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
-                        PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
+                        PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310;
     pcc->msr_mask = (1ull << MSR_SF) |
                     (1ull << MSR_HV) |
                     (1ull << MSR_TM) |